{"id":"https://openalex.org/W3143952996","doi":"https://doi.org/10.1109/aspdac.2010.5419798","title":"Incremental high-level synthesis","display_name":"Incremental high-level synthesis","publication_year":2010,"publication_date":"2010-01-01","ids":{"openalex":"https://openalex.org/W3143952996","doi":"https://doi.org/10.1109/aspdac.2010.5419798","mag":"3143952996"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2010.5419798","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2010.5419798","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050365912","display_name":"Luciano Lavagno","orcid":"https://orcid.org/0000-0002-9762-6522"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Luciano Lavagno","raw_affiliation_strings":["Cadence Design Systems, Inc., USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Inc., USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069752974","display_name":"A. Kondratyev","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alex Kondratyev","raw_affiliation_strings":["Cadence Design Systems, Inc., USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Inc., USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112718420","display_name":"Yosinori Watanabe","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yosinori Watanabe","raw_affiliation_strings":["Cadence Design Systems, Inc., USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Inc., USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103136845","display_name":"Qiang Zhu","orcid":"https://orcid.org/0000-0001-7094-9236"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Qiang Zhu","raw_affiliation_strings":["Cadence Design Systems, Inc., USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Inc., USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112311250","display_name":"Mototsugu Fujii","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Mototsugu Fujii","raw_affiliation_strings":["Renesas Technology Corporation, Japan"],"affiliations":[{"raw_affiliation_string":"Renesas Technology Corporation, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020848962","display_name":"Mitsuru Tatesawa","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Mitsuru Tatesawa","raw_affiliation_strings":["Renesas Technology Corporation, Japan"],"affiliations":[{"raw_affiliation_string":"Renesas Technology Corporation, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005190614","display_name":"Noriyasu Nakayama","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Noriyasu Nakayama","raw_affiliation_strings":["Fujitsu Advanced Technologies Limited, China"],"affiliations":[{"raw_affiliation_string":"Fujitsu Advanced Technologies Limited, China","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5050365912"],"corresponding_institution_ids":["https://openalex.org/I66217453"],"apc_list":null,"apc_paid":null,"fwci":0.2497,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.62763805,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"26","issue":null,"first_page":"701","last_page":"706"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.9264484643936157},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.763080358505249},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7102178931236267},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5714025497436523},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5699856281280518},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5482677221298218},{"id":"https://openalex.org/keywords/design-cycle","display_name":"Design cycle","score":0.5180070996284485},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3839417099952698},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.3523164689540863},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33339789509773254},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2854793071746826},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.23673811554908752},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.21419724822044373},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.13142788410186768},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12975004315376282},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.126033753156662}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9264484643936157},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.763080358505249},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7102178931236267},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5714025497436523},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5699856281280518},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5482677221298218},{"id":"https://openalex.org/C2982740150","wikidata":"https://www.wikidata.org/wiki/Q5249230","display_name":"Design cycle","level":2,"score":0.5180070996284485},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3839417099952698},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3523164689540863},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33339789509773254},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2854793071746826},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.23673811554908752},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.21419724822044373},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.13142788410186768},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12975004315376282},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.126033753156662},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2010.5419798","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2010.5419798","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1777852485","https://openalex.org/W2010541316","https://openalex.org/W2115118594","https://openalex.org/W2124779745","https://openalex.org/W2130200371","https://openalex.org/W2132705003","https://openalex.org/W2155220566","https://openalex.org/W2295683841","https://openalex.org/W6696851094"],"related_works":["https://openalex.org/W4235515009","https://openalex.org/W2171413119","https://openalex.org/W2123076670","https://openalex.org/W1557016741","https://openalex.org/W2126475478","https://openalex.org/W2543290882","https://openalex.org/W1964556228","https://openalex.org/W2540275465","https://openalex.org/W3143952996","https://openalex.org/W2030628830"],"abstract_inverted_index":{"The":[0,139],"widespread":[1],"acceptance":[2],"of":[3,28],"High-level":[4],"synthesis":[5,54,156],"as":[6,78,81,110,112,154,158],"a":[7],"mainstream":[8],"tool":[9,107,140],"mostly":[10],"depends":[11],"on":[12],"its":[13],"tight":[14],"integration":[15],"with":[16,77],"the":[17,26,49,61,66,69,74,84,101,106,114,146,149,161,165],"following":[18],"RTL-to-GDSII":[19],"design":[20,50,163],"flow.":[21],"A":[22],"key":[23],"aspect":[24],"is":[25,71],"handling":[27],"so-called":[29],"Engineering":[30],"Change":[31],"Orders":[32],"(ECOs),":[33],"i.e.":[34],"minor":[35],"changes":[36],"required":[37,75],"to":[38,57,72,83,108,134,164],"fix":[39],"small":[40],"functional":[41],"bugs":[42],"or":[43],"meet":[44],"performance":[45],"requirements":[46],"late":[47],"in":[48,65,125],"cycle.":[51],"Traditional":[52],"high-level":[53],"has":[55],"attempted":[56],"optimize":[58],"at":[59],"best":[60],"output":[62],"logic.":[63],"However,":[64],"ECO":[67,150,166],"scenario":[68],"goal":[70],"implement":[73,123],"change":[76],"few":[79],"modifications":[80],"possible":[82,113,159],"RTL,":[85],"logic":[86],"netlist,":[87],"placed":[88],"netlist":[89],"and":[90,122,148,152],"layout.":[91],"In":[92],"this":[93],"paper":[94],"we":[95],"show":[96],"how,":[97],"by":[98,105],"judiciously":[99],"changing":[100],"internal":[102],"databases":[103],"used":[104],"match":[109],"much":[111],"original":[115,147,162],"design,":[116,151],"one":[117],"can":[118],"achieve":[119],"minimal":[120],"impact":[121],"ECOs":[124],"truly":[126],"incremental":[127],"mode,":[128],"while":[129],"full-blow":[130],"re-synthesis":[131],"would":[132],"lead":[133],"massive":[135],"unnecessary":[136],"downstream":[137],"changes.":[138],"essentially":[141],"matches":[142],"source":[143],"constructs":[144],"between":[145],"copies":[153],"many":[155],"decisions":[157],"from":[160],"design.":[167]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
