{"id":"https://openalex.org/W3144063603","doi":"https://doi.org/10.1109/aspdac.2010.5419686","title":"On process-aware 1-D standard cell design","display_name":"On process-aware 1-D standard cell design","publication_year":2010,"publication_date":"2010-01-01","ids":{"openalex":"https://openalex.org/W3144063603","doi":"https://doi.org/10.1109/aspdac.2010.5419686","mag":"3144063603"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2010.5419686","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2010.5419686","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100461085","display_name":"Hongbo Zhang","orcid":"https://orcid.org/0000-0001-7259-5419"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Hongbo Zhang","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053378706","display_name":"Martin D. F. Wong","orcid":"https://orcid.org/0000-0001-8274-9688"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Martin D.F. Wong","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061862022","display_name":"Kai-Yuan Chao","orcid":"https://orcid.org/0009-0006-1057-1319"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kai-Yuan Chao","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100461085"],"corresponding_institution_ids":["https://openalex.org/I157725225"],"apc_list":null,"apc_paid":null,"fwci":2.3091,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.89525887,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"7271","issue":null,"first_page":"838","last_page":"842"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-for-manufacturability","display_name":"Design for manufacturability","score":0.959283709526062},{"id":"https://openalex.org/keywords/lithography","display_name":"Lithography","score":0.6680961847305298},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.649044394493103},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.63758385181427},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.6094063520431519},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.5920307636260986},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5838974714279175},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.484391987323761},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.47537389397621155},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.4738374650478363},{"id":"https://openalex.org/keywords/line","display_name":"Line (geometry)","score":0.452604204416275},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.434365451335907},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4083338975906372},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34574398398399353},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20162555575370789},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.1756841242313385},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.17398428916931152},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14797309041023254},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10804858803749084},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10642102360725403},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.1053701639175415}],"concepts":[{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.959283709526062},{"id":"https://openalex.org/C204223013","wikidata":"https://www.wikidata.org/wiki/Q133036","display_name":"Lithography","level":2,"score":0.6680961847305298},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.649044394493103},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.63758385181427},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.6094063520431519},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.5920307636260986},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5838974714279175},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.484391987323761},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.47537389397621155},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.4738374650478363},{"id":"https://openalex.org/C198352243","wikidata":"https://www.wikidata.org/wiki/Q37105","display_name":"Line (geometry)","level":2,"score":0.452604204416275},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.434365451335907},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4083338975906372},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34574398398399353},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20162555575370789},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.1756841242313385},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.17398428916931152},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14797309041023254},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10804858803749084},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10642102360725403},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.1053701639175415},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2010.5419686","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2010.5419686","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5199999809265137}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1975356894","https://openalex.org/W2012552926","https://openalex.org/W2016669084","https://openalex.org/W2057104060","https://openalex.org/W2100344939","https://openalex.org/W3139835941","https://openalex.org/W3149765056","https://openalex.org/W6644321068","https://openalex.org/W6653931798","https://openalex.org/W6654546935","https://openalex.org/W6674862444","https://openalex.org/W6680636136"],"related_works":["https://openalex.org/W1979360617","https://openalex.org/W2975406511","https://openalex.org/W4251264894","https://openalex.org/W2072989701","https://openalex.org/W3192656014","https://openalex.org/W2388589331","https://openalex.org/W1569991298","https://openalex.org/W2520621519","https://openalex.org/W2366713167","https://openalex.org/W2097103468"],"abstract_inverted_index":{"When":[0],"VLSI":[1],"technology":[2],"scales":[3],"down":[4],"to":[5,19,32,51,73],"sub-40nm":[6],"process":[7],"node,":[8],"systematic":[9],"variation":[10],"introduced":[11],"by":[12],"the":[13,20,25,53,56,64,76,86],"lithography":[14],"is":[15,71],"a":[16,34],"persistent":[17],"challenge":[18],"manufacturability.":[21],"The":[22],"limitation":[23],"of":[24],"resolution":[26],"enhancement":[27],"technologies":[28],"(RETs)":[29],"forces":[30],"people":[31],"adopt":[33],"regular":[35],"cell":[36,45],"design":[37],"methodology.":[38],"In":[39],"this":[40],"paper,":[41],"targeted":[42],"on":[43,63,94,106],"1D":[44],"design,":[46],"we":[47],"use":[48],"simulation":[49],"data":[50],"analyze":[52],"relationship":[54],"between":[55],"line-end":[57],"gap":[58,65,87],"distribution":[59,66,88],"and":[60,79,89,96],"printability.":[61,91],"Based":[62],"preferences,":[67],"an":[68],"optimal":[69],"algorithm":[70],"provided":[72],"efficiently":[74],"extend":[75],"line":[77],"ends":[78],"insert":[80],"dummies,":[81],"which":[82],"will":[83],"significantly":[84],"improve":[85],"help":[90],"Experimental":[92],"results":[93],"45nm":[95],"32nm":[97],"processes":[98],"show":[99],"that":[100],"significant":[101],"improvement":[102],"can":[103],"be":[104],"obtained":[105],"edge":[107],"placement":[108],"error":[109],"(EPE).":[110]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}