{"id":"https://openalex.org/W3143675127","doi":"https://doi.org/10.1109/aspdac.2009.4796500","title":"Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform","display_name":"Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform","publication_year":2009,"publication_date":"2009-01-01","ids":{"openalex":"https://openalex.org/W3143675127","doi":"https://doi.org/10.1109/aspdac.2009.4796500","mag":"3143675127"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2009.4796500","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2009.4796500","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041853964","display_name":"Antonino Tumeo","orcid":"https://orcid.org/0000-0001-9452-120X"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Antonino Tumeo","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085898687","display_name":"Marco Branca","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Branca","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020417718","display_name":"Lorenzo Camerini","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Lorenzo Camerini","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049942674","display_name":"Marco Ceriani","orcid":"https://orcid.org/0000-0002-4498-5863"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Ceriani","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038294114","display_name":"Matteo Monchiero","orcid":null},"institutions":[{"id":"https://openalex.org/I1324840837","display_name":"Hewlett-Packard (United States)","ror":"https://ror.org/059rn9488","country_code":"US","type":"company","lineage":["https://openalex.org/I1324840837"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Matteo Monchiero","raw_affiliation_strings":["HP Laboratories, Palo Alto, USA"],"affiliations":[{"raw_affiliation_string":"HP Laboratories, Palo Alto, USA","institution_ids":["https://openalex.org/I1324840837"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077005193","display_name":"Gianluca Palermo","orcid":"https://orcid.org/0000-0001-7955-8012"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gianluca Palermo","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028565685","display_name":"Fabrizio Ferrandi","orcid":"https://orcid.org/0000-0003-0301-4419"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Fabrizio Ferrandi","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014181688","display_name":"Donatella Sciuto","orcid":"https://orcid.org/0000-0001-9030-6940"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Donatella Sciuto","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5041853964"],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":1.3191,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.82900839,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"317","last_page":"322"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8510150909423828},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.7416340112686157},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.6838961243629456},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.6792094707489014},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.6486565470695496},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6233782172203064},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.5291690826416016},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5133585333824158},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4991765022277832},{"id":"https://openalex.org/keywords/focus","display_name":"Focus (optics)","score":0.46374425292015076},{"id":"https://openalex.org/keywords/rapid-prototyping","display_name":"Rapid prototyping","score":0.44412940740585327},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4313841760158539},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34663933515548706},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15925544500350952}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8510150909423828},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.7416340112686157},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.6838961243629456},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.6792094707489014},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6486565470695496},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6233782172203064},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.5291690826416016},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5133585333824158},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4991765022277832},{"id":"https://openalex.org/C192209626","wikidata":"https://www.wikidata.org/wiki/Q190909","display_name":"Focus (optics)","level":2,"score":0.46374425292015076},{"id":"https://openalex.org/C2780395129","wikidata":"https://www.wikidata.org/wiki/Q1128971","display_name":"Rapid prototyping","level":2,"score":0.44412940740585327},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4313841760158539},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34663933515548706},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15925544500350952},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2009.4796500","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2009.4796500","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6399999856948853,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1493456587","https://openalex.org/W1552339311","https://openalex.org/W1582084802","https://openalex.org/W1686420892","https://openalex.org/W2037915256","https://openalex.org/W2063909201","https://openalex.org/W2093795491","https://openalex.org/W2114822644","https://openalex.org/W2162097970","https://openalex.org/W2165100134","https://openalex.org/W3141634429","https://openalex.org/W3144802551","https://openalex.org/W6632826221","https://openalex.org/W6637151178"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2045183646","https://openalex.org/W2162409446","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W2316202402","https://openalex.org/W2268046897","https://openalex.org/W2033862586"],"abstract_inverted_index":{"Multiprocessors":[0],"on":[1,34,56,132],"a":[2,58,68,73,82,147],"chip":[3,24],"are":[4],"the":[5,17,27,35,44,49,96,99,122,127,133,137,141,144],"reality":[6],"of":[7,29,40,51,81,84,98,143,146],"these":[8,76],"days.":[9],"Semiconductor":[10],"industry":[11],"has":[12],"recognized":[13],"this":[14,30,53],"approach":[15],"as":[16],"most":[18],"efficient":[19],"in":[20,140],"order":[21],"to":[22,47,62,129],"exploit":[23],"resources,":[25],"but":[26],"success":[28],"paradigm":[31],"heavily":[32],"relies":[33],"efficiency":[36],"and":[37,72,86,101,103,108,125],"widespread":[38],"diffusion":[39],"parallel":[41],"software.":[42],"Among":[43],"many":[45],"techniques":[46],"express":[48],"parallelism":[50],"applications,":[52],"paper":[54],"focuses":[55],"pipelining,":[57],"technique":[59],"well":[60],"suited":[61],"data-intensive":[63],"multimedia":[64,107],"applications.":[65,77],"We":[66,90],"introduce":[67],"prototyping":[69],"platform":[70,79],"(FPGA-based)":[71],"methodology":[74],"for":[75],"Our":[78,119],"consists":[80],"mix":[83],"standard":[85],"custom":[87],"heterogeneous":[88],"cores.":[89],"discuss":[91],"several":[92],"case":[93],"studies,":[94],"analyzing":[95],"interaction":[97],"architecture":[100],"applications":[102,110],"we":[104],"show":[105],"that":[106],"telecommunication":[109],"with":[111],"unbalanced":[112],"pipeline":[113],"stages":[114],"can":[115],"be":[116],"easily":[117],"deployed.":[118],"framework":[120],"eases":[121],"development":[123],"cycle":[124],"enables":[126],"developers":[128],"focus":[130],"directly":[131],"problems":[134],"posed":[135],"by":[136],"programming":[138],"model":[139],"direction":[142],"implementation":[145],"production":[148],"system.":[149]},"counts_by_year":[{"year":2018,"cited_by_count":3},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}