{"id":"https://openalex.org/W2095722061","doi":"https://doi.org/10.1109/aspdac.2008.4484061","title":"Panel: Best ways to use billions of devices on a chip","display_name":"Panel: Best ways to use billions of devices on a chip","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W2095722061","doi":"https://doi.org/10.1109/aspdac.2008.4484061","mag":"2095722061"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2008.4484061","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2008.4484061","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111505799","display_name":"Grant Martin","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Grant Martin","raw_affiliation_strings":["Tensilica, Inc., Santa Clara, CA, USA","Tensilica Inc., Santa Clara,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tensilica, Inc., Santa Clara, CA, USA","institution_ids":[]},{"raw_affiliation_string":"Tensilica Inc., Santa Clara,","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":["https://openalex.org/A5111505799"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"801","last_page":"802"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9879999756813049,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7048486471176147},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5868896245956421},{"id":"https://openalex.org/keywords/moores-law","display_name":"Moore's law","score":0.5563133955001831},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5348844528198242},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5339722633361816},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5263991355895996},{"id":"https://openalex.org/keywords/variety","display_name":"Variety (cybernetics)","score":0.520183801651001},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4831054210662842},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.47467494010925293},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46304160356521606},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4599302411079407},{"id":"https://openalex.org/keywords/best-practice","display_name":"Best practice","score":0.4517958164215088},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.41854211688041687},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.22079694271087646},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21065372228622437},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.20165669918060303},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16111916303634644},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12228396534919739}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7048486471176147},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5868896245956421},{"id":"https://openalex.org/C206891323","wikidata":"https://www.wikidata.org/wiki/Q178655","display_name":"Moore's law","level":2,"score":0.5563133955001831},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5348844528198242},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5339722633361816},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5263991355895996},{"id":"https://openalex.org/C136197465","wikidata":"https://www.wikidata.org/wiki/Q1729295","display_name":"Variety (cybernetics)","level":2,"score":0.520183801651001},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4831054210662842},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.47467494010925293},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46304160356521606},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4599302411079407},{"id":"https://openalex.org/C184356942","wikidata":"https://www.wikidata.org/wiki/Q830382","display_name":"Best practice","level":2,"score":0.4517958164215088},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.41854211688041687},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.22079694271087646},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21065372228622437},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.20165669918060303},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16111916303634644},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12228396534919739},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C187736073","wikidata":"https://www.wikidata.org/wiki/Q2920921","display_name":"Management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2008.4484061","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2008.4484061","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8799999952316284,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2326041751","https://openalex.org/W1990262300","https://openalex.org/W2328312183","https://openalex.org/W1966241942","https://openalex.org/W2079942837","https://openalex.org/W1994557265","https://openalex.org/W2827669121","https://openalex.org/W2368718671","https://openalex.org/W2103744996","https://openalex.org/W2951722031"],"abstract_inverted_index":{"We":[0],"all":[1,77],"know":[2],"that":[3,111,248],"Moore's":[4],"law":[5],"is":[6],"good":[7,288],"for":[8,76,157,164],"at":[9,90],"least":[10],"a":[11,44,87,169,190,287],"few":[12],"more":[13,62,64,131,145,147],"generations":[14],"of":[15,29,48,78,81,171,187],"silicon":[16,308],"process,":[17],"and":[18,63,66,94,101,120,126,138,146,151,162,176,179,202,215,225,242,261,265],"this":[19],"will":[20,192,229,251,284],"give":[21,252],"rise":[22],"to":[23,43,84,104,115,133,173,196,237,246,256,259,266,278,290,295],"many":[24,109],"integrated":[25],"circuits":[26],"having":[27],"billions":[28,80,121,186],"transistors":[30,46,188],"on":[31,189,222,233],"them.":[32],"The":[33],"leading":[34],"45":[35],"nm":[36,96],"processors":[37],"being":[38],"announced":[39],"are":[40],"getting":[41],"close":[42],"billion":[45],"as":[47,273,303],"2007.":[49],"But":[50],"how":[51],"can":[52,112,206],"we":[53,207,304],"best":[54,116,208,235,244],"use":[55,75,117,279],"these":[56,79,263,280],"devices":[57],"in":[58],"the":[59,73,108,118,135,183,234,243,257,275,282,292],"future?":[60],"Integrating":[61],"features":[65],"functions":[67],"onto":[68],"SoCs":[69],"may":[70,97],"not":[71],"be":[72,105,113,286,301],"optimal":[74],"resources.":[82],"Indeed,":[83],"even":[85],"have":[86],"working":[88],"device":[89],"45,":[91],"32,":[92],"22":[93],"16":[95],"require":[98],"new":[99,102],"architectures":[100,143,163],"structures":[103,153,156,161],"incorporated.":[106],"Among":[107],"ideas":[110,264],"advanced":[114],"'billions":[119],"served'":[122],"are:":[123],"(1)":[124],"multicore":[125],"multiprocessor":[127,142],"systems":[128],"(2)":[129],"yet":[130],"memory,":[132],"hold":[134],"embedded":[136],"software":[137],"data":[139],"required":[140],"by":[141],"(3)":[144],"elaborate":[148],"on-chip":[149],"interconnect":[150],"network":[152],"(4)":[154],"redundant":[155],"defect":[158],"tolerance":[159],"(5)":[160],"dynamic":[165],"error":[166],"recovery":[167],"(6)":[168],"variety":[170],"schemes":[172],"allow":[174],"lower":[175,177],"power":[178],"energy":[180],"consumption":[181],"At":[182],"same":[184],"time,":[185],"chip":[191],"pose":[193],"increasing":[194],"challenges":[195],"our":[197],"design":[198,203],"methodologies,":[199],"integration":[200],"approaches":[201],"tools.":[204],"How":[205],"conceive":[209],"of,":[210],"architect,":[211],"design,":[212],"integrate,":[213],"verify":[214],"manufacture":[216],"such":[217],"devices?":[218],"This":[219],"panel":[220,283],"draws":[221],"several":[223],"academic":[224],"industry":[226],"experts":[227],"who":[228],"discuss":[230,262,291],"their":[231,268],"views":[232],"things":[236],"integrate":[238],"into":[239],"future":[240],"ICs,":[241],"ways":[245,277,294],"do":[247],"integration.":[249],"It":[250],"an":[253],"excellent":[254],"opportunity":[255,289],"audience":[258],"challenge":[260],"advocate":[267],"own":[269],"views.":[270],"As":[271],"well":[272],"considering":[274],"'best'":[276],"resources,":[281],"also":[285],"'worst'":[293],"proceed.":[296],"What":[297],"architectural":[298],"dead-ends":[299],"should":[300],"avoided":[302],"move":[305],"through":[306],"each":[307],"process":[309],"generation?":[310]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}