{"id":"https://openalex.org/W4242766712","doi":"https://doi.org/10.1109/aspdac.2008.4484046","title":"High performance current-mode differential logic","display_name":"High performance current-mode differential logic","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W4242766712","doi":"https://doi.org/10.1109/aspdac.2008.4484046"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2008.4484046","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2008.4484046","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082958276","display_name":"Ling Zhang","orcid":"https://orcid.org/0000-0002-5578-8574"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ling Zhang","raw_affiliation_strings":["Department Computer Science & Engineering, University of California, San Diego, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department Computer Science & Engineering, University of California, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100405330","display_name":"Jianhua Liu","orcid":"https://orcid.org/0000-0002-5856-8702"},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jianhua Liu","raw_affiliation_strings":["Altera Corporation, San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Altera Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I22433950"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100561504","display_name":"Haikun Zhu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Haikun Zhu","raw_affiliation_strings":["Qualcomm, Inc., San Diego, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm, Inc., San Diego, CA, USA","institution_ids":["https://openalex.org/I4210087596"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039615312","display_name":"Chung\u2010Kuan Cheng","orcid":"https://orcid.org/0000-0002-9865-8390"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chung-Kuan Cheng","raw_affiliation_strings":["Department Computer Science & Engineering, University of California, San Diego, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department Computer Science & Engineering, University of California, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002405139","display_name":"Masanori Hashimoto","orcid":"https://orcid.org/0000-0002-0377-2108"},"institutions":[{"id":"https://openalex.org/I98285908","display_name":"The University of Osaka","ror":"https://ror.org/035t8zc32","country_code":"JP","type":"education","lineage":["https://openalex.org/I98285908"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masanori Hashimoto","raw_affiliation_strings":["Department Information Systems Engineering, Osaka University, Osaka, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department Information Systems Engineering, Osaka University, Osaka, Japan","institution_ids":["https://openalex.org/I98285908"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"720","last_page":"725"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.7062139511108398},{"id":"https://openalex.org/keywords/current-mode-logic","display_name":"Current-mode logic","score":0.6664484739303589},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.659501314163208},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6413429379463196},{"id":"https://openalex.org/keywords/pull-up-resistor","display_name":"Pull-up resistor","score":0.6322336196899414},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.5947794914245605},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5914167761802673},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.5856099128723145},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5766448974609375},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5373373031616211},{"id":"https://openalex.org/keywords/emitter-coupled-logic","display_name":"Emitter-coupled logic","score":0.5231186747550964},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4941385090351105},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.4906410276889801},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.46282416582107544},{"id":"https://openalex.org/keywords/integrated-injection-logic","display_name":"Integrated injection logic","score":0.45733457803726196},{"id":"https://openalex.org/keywords/swing","display_name":"Swing","score":0.4527875781059265},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4458768367767334},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4374963045120239},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.42196860909461975},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4113593101501465},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3588681221008301},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.31326812505722046},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25884637236595154},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.25825709104537964},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.2514722943305969},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.12478390336036682}],"concepts":[{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.7062139511108398},{"id":"https://openalex.org/C2780295579","wikidata":"https://www.wikidata.org/wiki/Q5195108","display_name":"Current-mode logic","level":3,"score":0.6664484739303589},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.659501314163208},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6413429379463196},{"id":"https://openalex.org/C61818909","wikidata":"https://www.wikidata.org/wiki/Q1987617","display_name":"Pull-up resistor","level":5,"score":0.6322336196899414},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.5947794914245605},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5914167761802673},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.5856099128723145},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5766448974609375},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5373373031616211},{"id":"https://openalex.org/C11644886","wikidata":"https://www.wikidata.org/wiki/Q173552","display_name":"Emitter-coupled logic","level":5,"score":0.5231186747550964},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4941385090351105},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.4906410276889801},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.46282416582107544},{"id":"https://openalex.org/C159903706","wikidata":"https://www.wikidata.org/wiki/Q173574","display_name":"Integrated injection logic","level":5,"score":0.45733457803726196},{"id":"https://openalex.org/C65655974","wikidata":"https://www.wikidata.org/wiki/Q14867674","display_name":"Swing","level":2,"score":0.4527875781059265},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4458768367767334},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4374963045120239},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.42196860909461975},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4113593101501465},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3588681221008301},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.31326812505722046},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25884637236595154},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.25825709104537964},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.2514722943305969},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.12478390336036682},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2008.4484046","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2008.4484046","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6700000166893005}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1985315099","https://openalex.org/W2000260960","https://openalex.org/W2083356842","https://openalex.org/W2100280798","https://openalex.org/W2102653533","https://openalex.org/W2135955108","https://openalex.org/W2141849037","https://openalex.org/W2144278137","https://openalex.org/W2145173415","https://openalex.org/W2149397818","https://openalex.org/W2152907825","https://openalex.org/W2154363431","https://openalex.org/W2155199871"],"related_works":["https://openalex.org/W2114869156","https://openalex.org/W1594756605","https://openalex.org/W2130510302","https://openalex.org/W1968699962","https://openalex.org/W2084524856","https://openalex.org/W3146642485","https://openalex.org/W2102653533","https://openalex.org/W1538422785","https://openalex.org/W2112242076","https://openalex.org/W4242766712"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,31],"new":[4],"logic":[5,10,121],"style,":[6],"named":[7],"Current-Mode":[8],"Differential":[9],"(CMDL),":[11],"that":[12,77],"achieves":[13],"both":[14],"high":[15],"operating":[16,100],"speed":[17,103],"and":[18,122],"low":[19,41],"power":[20,130],"consumption.":[21],"Inspired":[22],"by":[23,87,134],"the":[24,35,45,57,67,78,129],"low-voltage":[25],"swing":[26,42],"(LVS)":[27],"logic,":[28,106],"CMDL":[29,79,107,127],"uses":[30],"shunt":[32,52],"resistor":[33],"at":[34,101],"differential":[36],"output":[37],"to":[38,47,60,112,119,136],"obtain":[39],"constant":[40],"signal":[43],"without":[44],"need":[46],"reset":[48,70],"low.":[49],"Furthermore,":[50],"conditional":[51],"transistors":[53],"are":[54],"used":[55],"for":[56,82],"internal":[58],"nodes":[59],"prevent":[61],"high-voltage":[62],"swing,":[63],"thus":[64],"entirely":[65],"eliminate":[66],"power-hungry":[68],"clocked":[69],"network":[71],"in":[72,93],"LVS":[73,105,123,133],"circuits.":[74],"We":[75],"show":[76],"is":[80],"suitable":[81],"high-end":[83],"microprocessor":[84],"integer":[85],"core":[86],"providing":[88],"three":[89],"datapath":[90],"modules":[91],"implemented":[92],"CMDL.":[94],"Our":[95],"simulation":[96],"results":[97],"indicate":[98],"that,":[99],"comparable":[102],"with":[104],"circuits":[108],"can":[109],"achieve":[110],"up":[111,135],"50%":[113],"reduction":[114],"of":[115,132],"delay-power":[116],"product":[117],"compared":[118],"CMOS":[120],"logic.":[124],"In":[125],"addition,":[126],"reduces":[128],"consumption":[131],"40%.":[137]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
