{"id":"https://openalex.org/W4240097130","doi":"https://doi.org/10.1109/aspdac.2008.4484018","title":"GECOM: Test data compression combined with all unknown response masking","display_name":"GECOM: Test data compression combined with all unknown response masking","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W4240097130","doi":"https://doi.org/10.1109/aspdac.2008.4484018"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2008.4484018","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2008.4484018","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056061175","display_name":"Youhua Shi","orcid":"https://orcid.org/0000-0002-1473-9776"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Youhua Shi","raw_affiliation_strings":["School of Fundamental Science and Engineering, Waseda University, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Fundamental Science and Engineering, Waseda University, Tokyo, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087516286","display_name":"Nozomu Togawa","orcid":"https://orcid.org/0000-0003-3400-3587"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Nozomu Togawa","raw_affiliation_strings":["School of Fundamental Science and Engineering, Waseda University, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Fundamental Science and Engineering, Waseda University, Tokyo, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061982025","display_name":"Masao Yanagisawa","orcid":"https://orcid.org/0000-0002-5168-3214"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masao Yanagisawa","raw_affiliation_strings":["School of Fundamental Science and Engineering, Waseda University, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Fundamental Science and Engineering, Waseda University, Tokyo, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109154058","display_name":"Tatsuo Ohtsuki","orcid":null},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tatsuo Ohtsuki","raw_affiliation_strings":["School of Fundamental Science and Engineering, Waseda University, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Fundamental Science and Engineering, Waseda University, Tokyo, Japan","institution_ids":["https://openalex.org/I150744194"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I150744194"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"577","last_page":"582"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9876999855041504,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.8977450728416443},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.8018416166305542},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6594623327255249},{"id":"https://openalex.org/keywords/masking","display_name":"Masking (illustration)","score":0.6005839705467224},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5592437386512756},{"id":"https://openalex.org/keywords/data-compression","display_name":"Data compression","score":0.533721923828125},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5037094950675964},{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.4831649661064148},{"id":"https://openalex.org/keywords/compression","display_name":"Compression (physics)","score":0.48288679122924805},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.47457364201545715},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.42763012647628784},{"id":"https://openalex.org/keywords/test-data","display_name":"Test data","score":0.41468751430511475},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.393258273601532},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.29567062854766846},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1629171073436737},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07686495780944824}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.8977450728416443},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.8018416166305542},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6594623327255249},{"id":"https://openalex.org/C2777402240","wikidata":"https://www.wikidata.org/wiki/Q6783436","display_name":"Masking (illustration)","level":2,"score":0.6005839705467224},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5592437386512756},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.533721923828125},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5037094950675964},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.4831649661064148},{"id":"https://openalex.org/C180016635","wikidata":"https://www.wikidata.org/wiki/Q2712821","display_name":"Compression (physics)","level":2,"score":0.48288679122924805},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.47457364201545715},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.42763012647628784},{"id":"https://openalex.org/C16910744","wikidata":"https://www.wikidata.org/wiki/Q7705759","display_name":"Test data","level":2,"score":0.41468751430511475},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.393258273601532},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.29567062854766846},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1629171073436737},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07686495780944824},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2008.4484018","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2008.4484018","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1560011026","https://openalex.org/W1576951655","https://openalex.org/W1592824829","https://openalex.org/W1627397376","https://openalex.org/W1676666806","https://openalex.org/W2038886877","https://openalex.org/W2099814124","https://openalex.org/W2101900253","https://openalex.org/W2105282021","https://openalex.org/W2135627440","https://openalex.org/W2136127440","https://openalex.org/W2138530143","https://openalex.org/W2149093111","https://openalex.org/W2153336129","https://openalex.org/W2165030600","https://openalex.org/W4230084852","https://openalex.org/W4248174041"],"related_works":["https://openalex.org/W2789883751","https://openalex.org/W2147986372","https://openalex.org/W1979305473","https://openalex.org/W2274367941","https://openalex.org/W1974621628","https://openalex.org/W3088373974","https://openalex.org/W2035832568","https://openalex.org/W1581610324","https://openalex.org/W2129124567","https://openalex.org/W2146547687"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"GECOM":[3,89,93,96,101,126,133,170],"technology,":[4],"a":[5,104],"novel":[6],"test":[7,14,16,35,129],"compression":[8,20,70],"method":[9,45],"with":[10,106],"seamless":[11],"integration":[12],"of":[13,40,92,167],"GEneration,":[15],"COmpression":[17],"(i.e.":[18],"integrated":[19],"on":[21,156],"scan":[22,30,67,109,139],"stimulus":[23],"and":[24,27,53,95,160],"masking":[25],"bits)":[26],"all":[28,147],"unknown":[29,48,78,149],"responses":[31,49,79,150],"Masking":[32],"for":[33,69,103,131],"manufacturing":[34],"cost":[36],"reduction.":[37],"Unlike":[38],"most":[39],"prior":[41],"methods,":[42],"the":[43,47,56,73,77,84,100,132,138,148,165,168],"proposed":[44,88,169],"considers":[46],"during":[50],"ATPG":[51,97,127],"procedure":[52],"selectively":[54],"encodes":[55],"specified":[57],"1":[58],"or":[59,64],"0":[60],"bits":[61],"(either":[62],"is":[63],"Os)":[65],"in":[66],"slices":[68],"while":[71],"at":[72],"same":[74],"time":[75],"masks":[76],"before":[80],"sending":[81],"them":[82],"to":[83],"response":[85],"compactor.":[86],"The":[87],"technology":[90],"consists":[91],"architecture":[94,134],"technique.":[98,171],"In":[99],"architecture,":[102],"circuit":[105],"N":[107],"internal":[108],"chains,":[110],"only":[111,137],"c":[112,116],"tester":[113],"channels,":[114],"where":[115],"=":[117],"[log":[118],"<inf":[119],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[120],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</inf>":[121],"N]":[122],"+2,":[123],"are":[124],"required.":[125],"generates":[128],"patterns":[130],"thus":[135],"not":[136],"inputs":[140],"could":[141],"be":[142,152],"efficiently":[143],"compressed":[144],"but":[145],"also":[146],"would":[151],"masked.":[153],"Experimental":[154],"results":[155],"both":[157],"benchmark":[158],"circuits":[159],"real":[161],"industrial":[162],"designs":[163],"indicated":[164],"effectiveness":[166]},"counts_by_year":[{"year":2018,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
