{"id":"https://openalex.org/W4248728220","doi":"https://doi.org/10.1109/aspdac.2008.4483919","title":"Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA","display_name":"Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W4248728220","doi":"https://doi.org/10.1109/aspdac.2008.4483919"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2008.4483919","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2008.4483919","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100849238","display_name":"Cheng-Tao Hsieh","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Cheng-Tao Hsieh","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016776689","display_name":"Jason Cong","orcid":"https://orcid.org/0000-0003-2887-6963"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jason Cong","raw_affiliation_strings":["Computer Science Department, University of California, Los Angeles, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science Department, University of California, Los Angeles, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037210004","display_name":"Zhiru Zhang","orcid":"https://orcid.org/0000-0002-0778-0308"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhiru Zhang","raw_affiliation_strings":["Computer Science Department, University of California, Los Angeles, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science Department, University of California, Los Angeles, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073382186","display_name":"Shih-Chieh Chang","orcid":"https://orcid.org/0000-0003-0717-6466"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shih-Chieh Chang","raw_affiliation_strings":["Computer Science Department, University of California, Los Angeles, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science Department, University of California, Los Angeles, USA","institution_ids":["https://openalex.org/I161318765"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100849238"],"corresponding_institution_ids":["https://openalex.org/I25846049"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.41943541,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/glitch","display_name":"Glitch","score":0.8862978219985962},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8604660034179688},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.7748576402664185},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7044234871864319},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5600202679634094},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5491837859153748},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.5456945300102234},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5409605503082275},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5213338732719421},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46854862570762634},{"id":"https://openalex.org/keywords/flip","display_name":"Flip","score":0.45811691880226135},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.41493868827819824},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4091668725013733},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.12283357977867126},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11396089196205139},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.06464162468910217}],"concepts":[{"id":"https://openalex.org/C191287063","wikidata":"https://www.wikidata.org/wiki/Q543281","display_name":"Glitch","level":3,"score":0.8862978219985962},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8604660034179688},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.7748576402664185},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7044234871864319},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5600202679634094},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5491837859153748},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5456945300102234},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5409605503082275},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5213338732719421},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46854862570762634},{"id":"https://openalex.org/C2776591724","wikidata":"https://www.wikidata.org/wiki/Q5459651","display_name":"Flip","level":3,"score":0.45811691880226135},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.41493868827819824},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4091668725013733},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.12283357977867126},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11396089196205139},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.06464162468910217},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C190283241","wikidata":"https://www.wikidata.org/wiki/Q14599311","display_name":"Apoptosis","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/aspdac.2008.4483919","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2008.4483919","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.581.7030","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.581.7030","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cecs.uci.edu/~papers/aspdac08/pdf/p10_1A-2.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.4300000071525574,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1264779954","https://openalex.org/W1977545325","https://openalex.org/W2024178767","https://openalex.org/W2046222814","https://openalex.org/W2097798204","https://openalex.org/W2111485030","https://openalex.org/W2111647467","https://openalex.org/W2131481230","https://openalex.org/W2146589686","https://openalex.org/W2147088458","https://openalex.org/W2149301478","https://openalex.org/W2150294650","https://openalex.org/W2151929849","https://openalex.org/W2155314350","https://openalex.org/W2156420848","https://openalex.org/W2160250623","https://openalex.org/W2170510975","https://openalex.org/W4237989062","https://openalex.org/W4241239131","https://openalex.org/W4248059597","https://openalex.org/W4249832276","https://openalex.org/W4250101586","https://openalex.org/W6627924737","https://openalex.org/W6674750846","https://openalex.org/W6676444686","https://openalex.org/W6684652846"],"related_works":["https://openalex.org/W221087158","https://openalex.org/W2915471777","https://openalex.org/W318263151","https://openalex.org/W3032425875","https://openalex.org/W2013870538","https://openalex.org/W2079261375","https://openalex.org/W2413132533","https://openalex.org/W2497152992","https://openalex.org/W2032201261","https://openalex.org/W1984520783"],"abstract_inverted_index":{"In":[0,15],"this":[1],"paper":[2],"we":[3,17,69],"discuss":[4],"optimizing":[5],"the":[6,19,26,43,51,59,84,107],"interconnect":[7],"power":[8,21,105],"of":[9,28,45,50,61,86],"designs":[10],"implemented":[11],"in":[12,31,54,103,106],"FPGA":[13,56],"platforms.":[14],"particular,":[16],"reduce":[18],"glitch":[20],"on":[22,94],"interconnects":[23],"associated":[24],"with":[25],"output":[27],"functional":[29],"units":[30],"a":[32,100],"design.":[33],"The":[34,89],"idea":[35],"is":[36],"to":[37,41,76,99],"activate":[38],"unused":[39],"flip-flops":[40,53,63],"block":[42],"propagation":[44],"glitches,":[46],"which":[47],"takes":[48],"advantage":[49],"abundant":[52],"modern":[55],"structures.":[57],"Since":[58],"activation":[60],"additional":[62],"may":[64],"cause":[65],"data":[66,79],"hazard":[67],"problems,":[68],"develop":[70],"several":[71],"effective":[72],"behavioral":[73],"synthesis":[74],"techniques":[75],"prevent":[77],"such":[78],"hazards.":[80],"We":[81],"also":[82],"study":[83],"optimality":[85],"our":[87,96],"techniques.":[88],"experimental":[90],"results":[91],"show":[92],"that":[93],"average,":[95],"methods":[97],"lead":[98],"28%":[101],"reduction":[102],"dynamic":[104],"Xilinx":[108],"Virtex-II":[109],"platform.":[110]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
