{"id":"https://openalex.org/W4231966658","doi":"https://doi.org/10.1109/aspdac.2006.1594768","title":"An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis","display_name":"An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis","publication_year":2006,"publication_date":"2006-03-22","ids":{"openalex":"https://openalex.org/W4231966658","doi":"https://doi.org/10.1109/aspdac.2006.1594768"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2006.1594768","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2006.1594768","pdf_url":null,"source":{"id":"https://openalex.org/S4363608292","display_name":"Asia and South Pacific Conference on Design Automation, 2006.","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia and South Pacific Conference on Design Automation, 2006.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100364291","display_name":"Xiaoying Wang","orcid":"https://orcid.org/0000-0002-2436-0807"},"institutions":[{"id":"https://openalex.org/I114090438","display_name":"Goethe University Frankfurt","ror":"https://ror.org/04cvxnb49","country_code":"DE","type":"education","lineage":["https://openalex.org/I114090438"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Xiaoying Wang","raw_affiliation_strings":["Department of Computer Science, University of Frankfurt am Main, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Frankfurt am Main, Germany","institution_ids":["https://openalex.org/I114090438"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061161722","display_name":"L. Hedrich","orcid":null},"institutions":[{"id":"https://openalex.org/I114090438","display_name":"Goethe University Frankfurt","ror":"https://ror.org/04cvxnb49","country_code":"DE","type":"education","lineage":["https://openalex.org/I114090438"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"L. Hedrich","raw_affiliation_strings":["Department of Computer Science, University of Frankfurt am Main, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Frankfurt am Main, Germany","institution_ids":["https://openalex.org/I114090438"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.8552,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.85143839,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"700","last_page":"705"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7395883202552795},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.6877956390380859},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.6257997155189514},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.5276390910148621},{"id":"https://openalex.org/keywords/symbolic-data-analysis","display_name":"Symbolic data analysis","score":0.5164449214935303},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5118483901023865},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.48327261209487915},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.47315701842308044},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.4423370063304901},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.41535085439682007},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.36131566762924194},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2533698081970215},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1496911644935608},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.13614332675933838},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1051906943321228},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.07845520973205566},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.07810267806053162}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7395883202552795},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.6877956390380859},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.6257997155189514},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.5276390910148621},{"id":"https://openalex.org/C65620979","wikidata":"https://www.wikidata.org/wiki/Q7661176","display_name":"Symbolic data analysis","level":2,"score":0.5164449214935303},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5118483901023865},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.48327261209487915},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.47315701842308044},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.4423370063304901},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.41535085439682007},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.36131566762924194},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2533698081970215},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1496911644935608},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.13614332675933838},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1051906943321228},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.07845520973205566},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07810267806053162},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2006.1594768","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2006.1594768","pdf_url":null,"source":{"id":"https://openalex.org/S4363608292","display_name":"Asia and South Pacific Conference on Design Automation, 2006.","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia and South Pacific Conference on Design Automation, 2006.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1536945048","https://openalex.org/W1565462788","https://openalex.org/W1566916904","https://openalex.org/W1999357165","https://openalex.org/W2039300364","https://openalex.org/W2096249093","https://openalex.org/W2096255496","https://openalex.org/W2141776905","https://openalex.org/W2169944292","https://openalex.org/W4236195134"],"related_works":["https://openalex.org/W2051646317","https://openalex.org/W2002347827","https://openalex.org/W4327500672","https://openalex.org/W1883347064","https://openalex.org/W2115397287","https://openalex.org/W2545603903","https://openalex.org/W1909865166","https://openalex.org/W2123531174","https://openalex.org/W2734663060","https://openalex.org/W2110273585"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,46,77,81],"method":[4,94],"of":[5,48,80,92],"design":[6],"automation":[7],"for":[8],"analog":[9],"circuits,":[10],"focusing":[11],"on":[12],"topology":[13,69],"generation":[14],"and":[15,71,90],"quick":[16],"performance":[17],"evaluation.":[18],"First":[19],"we":[20],"describe":[21],"mechanisms":[22],"to":[23,65,72],"generate":[24],"circuit":[25],"topologies":[26],"with":[27,45],"hierarchical":[28],"blocks.":[29],"Those":[30],"blocks":[31,41],"are":[32,52],"specialized":[33],"by":[34],"adding":[35],"terminal":[36],"information.":[37],"The":[38],"connection":[39],"between":[40],"is":[42],"in":[43,57],"compliance":[44],"set":[47],"synthesis":[49],"rules,":[50],"which":[51],"extracted":[53],"from":[54],"typical":[55],"schematics":[56],"the":[58,74,88],"literature.":[59],"Symbolic":[60],"analysis":[61],"has":[62],"been":[63],"used":[64],"select":[66],"an":[67],"appropriate":[68],"quickly":[70],"help":[73],"designer":[75],"gain":[76],"better":[78],"understanding":[79],"circuit's":[82],"behavior.":[83],"Finally,":[84],"experimental":[85],"results":[86],"show":[87],"creativity":[89],"efficiency":[91],"our":[93]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}