{"id":"https://openalex.org/W4239263106","doi":"https://doi.org/10.1109/aspdac.2006.1594726","title":"FSM-based transaction-level functional coverage for interface compliance verification","display_name":"FSM-based transaction-level functional coverage for interface compliance verification","publication_year":2006,"publication_date":"2006-03-22","ids":{"openalex":"https://openalex.org/W4239263106","doi":"https://doi.org/10.1109/aspdac.2006.1594726"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2006.1594726","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2006.1594726","pdf_url":null,"source":{"id":"https://openalex.org/S4363608292","display_name":"Asia and South Pacific Conference on Design Automation, 2006.","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia and South Pacific Conference on Design Automation, 2006.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060860528","display_name":"Man-Yun Su","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Man-Yun Su","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026831455","display_name":"Che-Hua Shih","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Che-Hua Shih","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107969989","display_name":"Juinn-Dar Huang","orcid":"https://orcid.org/0000-0001-5961-7863"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Juinn-Dar Huang","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111925764","display_name":"Jing-Yang Jou","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jing-Yang Jou","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5060860528"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.37869822,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"448","last_page":"453"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9926000237464905,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8244611024856567},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.673446536064148},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.6226110458374023},{"id":"https://openalex.org/keywords/database-transaction","display_name":"Database transaction","score":0.621843695640564},{"id":"https://openalex.org/keywords/completeness","display_name":"Completeness (order theory)","score":0.5939607620239258},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.5256791710853577},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.5062472224235535},{"id":"https://openalex.org/keywords/high-level-verification","display_name":"High-level verification","score":0.4578839838504791},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.4541546404361725},{"id":"https://openalex.org/keywords/protocol","display_name":"Protocol (science)","score":0.4374207556247711},{"id":"https://openalex.org/keywords/verification","display_name":"Verification","score":0.4168423116207123},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.36813926696777344},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3233222961425781},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12964513897895813},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.11408615112304688},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.08800822496414185}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8244611024856567},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.673446536064148},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.6226110458374023},{"id":"https://openalex.org/C75949130","wikidata":"https://www.wikidata.org/wiki/Q848010","display_name":"Database transaction","level":2,"score":0.621843695640564},{"id":"https://openalex.org/C17231256","wikidata":"https://www.wikidata.org/wiki/Q5156540","display_name":"Completeness (order theory)","level":2,"score":0.5939607620239258},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.5256791710853577},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.5062472224235535},{"id":"https://openalex.org/C187250869","wikidata":"https://www.wikidata.org/wiki/Q5754573","display_name":"High-level verification","level":5,"score":0.4578839838504791},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.4541546404361725},{"id":"https://openalex.org/C2780385302","wikidata":"https://www.wikidata.org/wiki/Q367158","display_name":"Protocol (science)","level":3,"score":0.4374207556247711},{"id":"https://openalex.org/C142284323","wikidata":"https://www.wikidata.org/wiki/Q7921323","display_name":"Verification","level":5,"score":0.4168423116207123},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.36813926696777344},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3233222961425781},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12964513897895813},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.11408615112304688},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.08800822496414185},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C142724271","wikidata":"https://www.wikidata.org/wiki/Q7208","display_name":"Pathology","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C204787440","wikidata":"https://www.wikidata.org/wiki/Q188504","display_name":"Alternative medicine","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2006.1594726","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2006.1594726","pdf_url":null,"source":{"id":"https://openalex.org/S4363608292","display_name":"Asia and South Pacific Conference on Design Automation, 2006.","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia and South Pacific Conference on Design Automation, 2006.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1602612484","https://openalex.org/W1873925915","https://openalex.org/W1972347219","https://openalex.org/W2041649123","https://openalex.org/W2059376007","https://openalex.org/W2064268191","https://openalex.org/W2110938665","https://openalex.org/W2123548394","https://openalex.org/W4231022782","https://openalex.org/W4232177410","https://openalex.org/W4233440324","https://openalex.org/W4244525710","https://openalex.org/W4251243624","https://openalex.org/W6664878660","https://openalex.org/W6666499770","https://openalex.org/W6676749828","https://openalex.org/W6678416002","https://openalex.org/W6684534873","https://openalex.org/W6684698445"],"related_works":["https://openalex.org/W3120172095","https://openalex.org/W2118572231","https://openalex.org/W2153955347","https://openalex.org/W3023586562","https://openalex.org/W2108860137","https://openalex.org/W2115488885","https://openalex.org/W3036403349","https://openalex.org/W2535719568","https://openalex.org/W2138343703","https://openalex.org/W2106507440"],"abstract_inverted_index":{"Interface":[0],"compliance":[1,44],"verification":[2,102],"plays":[3],"a":[4,16,32],"very":[5],"important":[6],"role":[7],"in":[8],"modern":[9],"SoC":[10],"designs.":[11],"In":[12,27],"order":[13],"to":[14,53,78],"perform":[15],"quantitative":[17],"analysis":[18],"of":[19,64,86,110],"simulation":[20],"completeness,":[21],"adequate":[22],"coverage":[23,40],"metrics":[24],"are":[25],"mandatory.":[26],"this":[28],"paper,":[29],"we":[30],"propose":[31],"finite":[33],"state":[34],"machine":[35],"(FSM)":[36],"based":[37],"transaction-level":[38],"functional":[39,55],"methodology":[41,97],"for":[42],"interface":[43,89],"verification.":[45,112],"A":[46],"language,":[47],"state-oriented":[48],"language":[49],"(SOL),":[50],"is":[51,74],"developed":[52],"specify":[54,79],"transactions":[56,81],"mainly":[57],"at":[58],"the":[59,83,87,95,101,108],"higher":[60],"FSM":[61,85],"level":[62],"instead":[63],"lower":[65],"logic":[66],"or":[67],"signal":[68],"level.":[69],"By":[70],"utilizing":[71],"SOL,":[72],"it":[73],"simple":[75],"and":[76],"rigorous":[77],"interesting":[80],"from":[82],"specification":[84],"target":[88],"protocol.":[90],"Experimental":[91],"results":[92],"show":[93],"that":[94],"proposed":[96],"can":[98],"effectively":[99],"improve":[100],"quality":[103],"as":[104,106],"well":[105],"increase":[107],"efficiency":[109],"regression":[111]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}