{"id":"https://openalex.org/W3149786325","doi":"https://doi.org/10.1109/aspdac.2006.1594703","title":"Spec-based flip-flop and latch repeater planning","display_name":"Spec-based flip-flop and latch repeater planning","publication_year":2006,"publication_date":"2006-03-22","ids":{"openalex":"https://openalex.org/W3149786325","doi":"https://doi.org/10.1109/aspdac.2006.1594703","mag":"3149786325"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2006.1594703","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2006.1594703","pdf_url":null,"source":{"id":"https://openalex.org/S4363608292","display_name":"Asia and South Pacific Conference on Design Automation, 2006.","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia and South Pacific Conference on Design Automation, 2006.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014292892","display_name":"Man Chung Hon","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Man Chung Hon","raw_affiliation_strings":["Intel Corportation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corportation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5014292892"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.43537513,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"27","issue":null,"first_page":"326","last_page":"331"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.7445685863494873},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.6487404108047485},{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.6025127172470093},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.599885106086731},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.570523202419281},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5404333472251892},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5175308585166931},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4455556869506836},{"id":"https://openalex.org/keywords/margin","display_name":"Margin (machine learning)","score":0.42480459809303284},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3470440208911896},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22290953993797302},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.12531614303588867},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09881353378295898}],"concepts":[{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.7445685863494873},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.6487404108047485},{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.6025127172470093},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.599885106086731},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.570523202419281},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5404333472251892},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5175308585166931},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4455556869506836},{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.42480459809303284},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3470440208911896},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22290953993797302},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.12531614303588867},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09881353378295898},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2006.1594703","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2006.1594703","pdf_url":null,"source":{"id":"https://openalex.org/S4363608292","display_name":"Asia and South Pacific Conference on Design Automation, 2006.","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia and South Pacific Conference on Design Automation, 2006.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1569461127","https://openalex.org/W2012173826","https://openalex.org/W2062530062","https://openalex.org/W2066408410","https://openalex.org/W2086184989","https://openalex.org/W2087656024","https://openalex.org/W2122769715","https://openalex.org/W2129943737","https://openalex.org/W2145964793","https://openalex.org/W2158098137","https://openalex.org/W2160252016","https://openalex.org/W2566091043","https://openalex.org/W4206143080","https://openalex.org/W4240722455","https://openalex.org/W6675008304","https://openalex.org/W6683978969"],"related_works":["https://openalex.org/W4315697128","https://openalex.org/W3102845713","https://openalex.org/W2971502891","https://openalex.org/W2262031297","https://openalex.org/W2024069812","https://openalex.org/W2733322820","https://openalex.org/W2056378213","https://openalex.org/W2045056374","https://openalex.org/W2298981088","https://openalex.org/W2163601309"],"abstract_inverted_index":{"Shrinking":[0],"process":[1],"geometries":[2],"and":[3,27,33,73,95],"frequency":[4],"scaling":[5],"give":[6],"rise":[7],"to":[8,24,29,44,56,82],"an":[9,51],"increasing":[10],"number":[11],"of":[12,47,97],"interconnects":[13],"that":[14,59],"require":[15],"multiple":[16],"clock":[17],"cycles.":[18],"This":[19],"paper":[20],"explores":[21],"efficient":[22],"techniques":[23],"insert":[25,57],"flip-flops":[26,58],"latches":[28,86],"meet":[30],"pre-determined":[31],"latency":[32],"margin":[34],"constraints":[35],"at":[36],"the":[37,65,93],"receivers.":[38],"Previous":[39],"approaches":[40],"push":[41],"timing":[42,62],"margins":[43,63],"either":[45],"ends":[46],"interconnect.":[48],"We":[49],"present":[50],"O(n":[52,78],"log":[53,79],"n)-time":[54,80],"algorithm":[55],"evens":[60],"out":[61],"across":[64],"entire":[66],"interconnect,":[67],"resulting":[68],"in":[69],"more":[70],"robust":[71],"designs":[72],"faster":[74],"design":[75],"convergence.":[76],"An":[77],"extension":[81],"handle":[83],"symmetric,":[84],"two-phases":[85],"is":[87],"also":[88],"presented.":[89],"Experimental":[90],"results":[91],"verify":[92],"correctness":[94],"practicality":[96],"our":[98],"approach.":[99]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}