{"id":"https://openalex.org/W4237886783","doi":"https://doi.org/10.1109/aspdac.2006.1594684","title":"Simultaneous block and I/O buffer floorplanning for flip-chip design","display_name":"Simultaneous block and I/O buffer floorplanning for flip-chip design","publication_year":2006,"publication_date":"2006-03-22","ids":{"openalex":"https://openalex.org/W4237886783","doi":"https://doi.org/10.1109/aspdac.2006.1594684"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.2006.1594684","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2006.1594684","pdf_url":null,"source":{"id":"https://openalex.org/S4363608292","display_name":"Asia and South Pacific Conference on Design Automation, 2006.","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia and South Pacific Conference on Design Automation, 2006.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083169084","display_name":"Chih-Yang Peng","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Chih-Yang Peng","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041529690","display_name":"Wen-Chang Chao","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wen-Chang Chao","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018371636","display_name":"Yao\u2010Wen Chang","orcid":"https://orcid.org/0000-0002-0564-5719"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yao-Wen Chang","raw_affiliation_strings":["Department of Electrical Engineering & Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering & Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036056549","display_name":"Jyh-Herng Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210112000","display_name":"Faraday Technology (Taiwan)","ror":"https://ror.org/021wyrx76","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210112000"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jyh-Herng Wang","raw_affiliation_strings":["Faraday Technology Corporation, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Faraday Technology Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210112000"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5083169084"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":0.6145,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.69516569,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"213","last_page":"218"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9641231298446655},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.7372967004776001},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.6725425720214844},{"id":"https://openalex.org/keywords/flip-chip","display_name":"Flip chip","score":0.6493797302246094},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6458778381347656},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6320266723632812},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6302443146705627},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5453842878341675},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5110141038894653},{"id":"https://openalex.org/keywords/block-size","display_name":"Block size","score":0.47314560413360596},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.43414169549942017},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3651336431503296},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2835232615470886},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.27647626399993896},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2728249430656433},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.26343226432800293}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9641231298446655},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.7372967004776001},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.6725425720214844},{"id":"https://openalex.org/C79072407","wikidata":"https://www.wikidata.org/wiki/Q432439","display_name":"Flip chip","level":4,"score":0.6493797302246094},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6458778381347656},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6320266723632812},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6302443146705627},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5453842878341675},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5110141038894653},{"id":"https://openalex.org/C41431624","wikidata":"https://www.wikidata.org/wiki/Q1053357","display_name":"Block size","level":3,"score":0.47314560413360596},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.43414169549942017},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3651336431503296},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2835232615470886},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.27647626399993896},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2728249430656433},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.26343226432800293},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.0},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C68928338","wikidata":"https://www.wikidata.org/wiki/Q131790","display_name":"Adhesive","level":3,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.2006.1594684","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.2006.1594684","pdf_url":null,"source":{"id":"https://openalex.org/S4363608292","display_name":"Asia and South Pacific Conference on Design Automation, 2006.","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Asia and South Pacific Conference on Design Automation, 2006.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4099999964237213,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1680287565","https://openalex.org/W1702702848","https://openalex.org/W1841949876","https://openalex.org/W1981846784","https://openalex.org/W1984954427","https://openalex.org/W1996746141","https://openalex.org/W2048796234","https://openalex.org/W2098488748","https://openalex.org/W2100740271","https://openalex.org/W2102502584","https://openalex.org/W2123354623","https://openalex.org/W2142356348","https://openalex.org/W2151190382","https://openalex.org/W2153770483","https://openalex.org/W2163961680","https://openalex.org/W2168126808","https://openalex.org/W2173471405","https://openalex.org/W4237664122","https://openalex.org/W4239854918","https://openalex.org/W4241644863","https://openalex.org/W6637124764","https://openalex.org/W6645737761","https://openalex.org/W6684879859"],"related_works":["https://openalex.org/W2124495928","https://openalex.org/W2097517502","https://openalex.org/W2129355781","https://openalex.org/W4363620137","https://openalex.org/W2096129555","https://openalex.org/W2161137937","https://openalex.org/W4233404530","https://openalex.org/W2052733504","https://openalex.org/W2152479836","https://openalex.org/W2103585921"],"abstract_inverted_index":{"The":[0,128,148,171],"flip-chip":[1,25,50,256],"package":[2],"gives":[3],"the":[4,14,20,29,45,49,57,67,78,82,95,108,117,125,139,152,158,188,191,196,203,219,246],"highest":[5],"chip":[6,153,197],"density":[7],"of":[8,19,24,59,81,116,184,190,238,241,253],"any":[9],"packaging":[10],"method":[11,92,225],"to":[12,93,106,142,195],"support":[13],"pad-limited":[15],"ASIC":[16],"design.":[17],"One":[18],"most":[21,180],"important":[22],"characteristics":[23],"designs":[26,257],"is":[27,226],"that":[28,66,242],"input/output":[30,60],"buffers":[31,61,105],"could":[32],"be":[33],"placed":[34,167],"anywhere":[35],"inside":[36,208],"a":[37,90,100,144,181,209,251],"chip.":[38],"In":[39],"this":[40],"paper,":[41],"we":[42,112,201],"first":[43,98],"introduce":[44],"floorplanning":[46],"problem":[47,109],"for":[48],"design":[51],"and":[52,62,72,102,119,124,157,165,229],"formulate":[53],"it":[54],"as":[55,75,77,211,213],"assigning":[56],"positions":[58],"first-stage/last-stage":[63],"blocks":[64,71,133,159,207],"so":[65],"path":[68],"length":[69],"between":[70],"bump":[73],"balls":[74],"well":[76,212],"delay":[79],"skew":[80],"paths":[83],"are":[84,160,166],"simultaneously":[85],"minimized.":[86],"We":[87,97],"then":[88],"present":[89],"hierarchical":[91],"solve":[94],"problem.":[96],"cluster":[99],"block":[101,193],"its":[103],"corresponding":[104],"reduce":[107],"size.":[110],"Then,":[111],"go":[113],"into":[114,154,162],"iterations":[115],"alternating":[118],"interacting":[120],"global":[121,129],"optimization":[122,130],"step":[123,131,150],"partitioning":[126,149],"step.":[127],"places":[132],"based":[134,221,249],"on":[135,250],"simulated":[136],"annealing":[137],"using":[138,245],"B*-tree":[140,220,247],"representation":[141],"minimize":[143],"given":[145,182],"cost":[146,237],"function.":[147],"dissects":[151],"two":[155,163,172],"subregions,":[156],"divided":[161],"groups":[164],"in":[168,214],"respective":[169],"subregions.":[170,216],"steps":[173],"repeat":[174],"until":[175],"each":[176],"subregion":[177,210],"contains":[178],"at":[179],"number":[183],"blocks,":[185],"defined":[186],"by":[187,205,244,259],"ratio":[189],"total":[192],"area":[194],"area.":[198],"At":[199],"last,":[200],"refine":[202],"floorplan":[204],"perturbing":[206],"different":[215],"Compared":[217],"with":[218,234],"floorplanner":[222],"alone,":[223,248],"our":[224],"more":[227],"efficient":[228],"obtains":[230],"significantly":[231],"better":[232],"results,":[233],"an":[235],"average":[236],"only":[239],"51.8%":[240],"obtained":[243],"set":[252],"real":[254],"industrial":[255],"provided":[258],"leading":[260],"companies":[261]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
