{"id":"https://openalex.org/W4212766237","doi":"https://doi.org/10.1109/asp-dac52403.2022.9712564","title":"Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models","display_name":"Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models","publication_year":2022,"publication_date":"2022-01-17","ids":{"openalex":"https://openalex.org/W4212766237","doi":"https://doi.org/10.1109/asp-dac52403.2022.9712564"},"language":"en","primary_location":{"id":"doi:10.1109/asp-dac52403.2022.9712564","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asp-dac52403.2022.9712564","pdf_url":null,"source":{"id":"https://openalex.org/S4363608500","display_name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018506021","display_name":"Yue Xing","orcid":"https://orcid.org/0000-0001-7422-3352"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yue Xing","raw_affiliation_strings":["Princeton University,Princeton,USA","Princeton University, Princeton, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Princeton University,Princeton,USA","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Princeton University, Princeton, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041231710","display_name":"Aarti Gupta","orcid":"https://orcid.org/0000-0001-6676-9400"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Aarti Gupta","raw_affiliation_strings":["Princeton University,Princeton,USA","Princeton University, Princeton, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Princeton University,Princeton,USA","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Princeton University, Princeton, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085975362","display_name":"Sharad Malik","orcid":"https://orcid.org/0000-0002-0837-5443"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sharad Malik","raw_affiliation_strings":["Princeton University,Princeton,USA","Princeton University, Princeton, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Princeton University,Princeton,USA","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Princeton University, Princeton, USA","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":null,"apc_paid":null,"fwci":1.3917,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.78020679,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"154","last_page":"159"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.837731122970581},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.7604255676269531},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.5893746018409729},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5182064175605774},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.4783060848712921},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4596187472343445},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.43649888038635254},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42452895641326904},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.355526864528656},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.30289164185523987},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.10847273468971252}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.837731122970581},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.7604255676269531},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5893746018409729},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5182064175605774},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.4783060848712921},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4596187472343445},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.43649888038635254},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42452895641326904},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.355526864528656},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.30289164185523987},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.10847273468971252},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asp-dac52403.2022.9712564","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asp-dac52403.2022.9712564","pdf_url":null,"source":{"id":"https://openalex.org/S4363608500","display_name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4000000059604645,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[{"id":"https://openalex.org/G4943376207","display_name":"XPS: FULL: Hardware Software Abstractions: Addressing Specification and Verification Gaps in Accelerator-Oriented Parallelism","funder_award_id":"1628926","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1741528175","https://openalex.org/W1983394510","https://openalex.org/W1985217339","https://openalex.org/W2020677373","https://openalex.org/W2024158551","https://openalex.org/W2141772875","https://openalex.org/W2143062031","https://openalex.org/W2151051752","https://openalex.org/W2544002786","https://openalex.org/W2932228771","https://openalex.org/W3027123178","https://openalex.org/W3092209569","https://openalex.org/W3184410788","https://openalex.org/W4238435901","https://openalex.org/W4288637392","https://openalex.org/W6637675132","https://openalex.org/W6820139873"],"related_works":["https://openalex.org/W122453572","https://openalex.org/W2466405623","https://openalex.org/W4250432526","https://openalex.org/W1998013902","https://openalex.org/W2101536355","https://openalex.org/W2171175484","https://openalex.org/W2151122729","https://openalex.org/W1980898636","https://openalex.org/W2045325972","https://openalex.org/W2141090099"],"abstract_inverted_index":{"Simulation-based":[0],"testing":[1],"has":[2,86],"been":[3,87],"the":[4,22,35,43,46,50,55,61,69,72,78,102,116,121,131,146,152,158,161,164,180],"workhorse":[5],"of":[6,37,45,71,104,151,183],"hardware":[7],"implementation":[8],"validation.":[9],"For":[10],"processors,":[11,108],"tandem":[12,84,139],"simulation":[13,51,85,140,166],"improves":[14],"test":[15],"and":[16,27,30,58,100,119,163,171],"debug":[17],"efficiency":[18],"by":[19,67],"cross-level":[20],"simulating":[21],"Instruction":[23],"Set":[24],"Architecture":[25],"(ISA)":[26],"RTL":[28,62,165],"models,":[29],"comparing":[31],"architectural-state":[32],"variables":[33],"at":[34,42,64],"end":[36,44],"each":[38],"instruction":[39],"rather":[40],"than":[41],"whole":[47],"trace.":[48],"Further,":[49,143],"may":[52],"start":[53],"with":[54],"ISA":[56,98],"model":[57,63],"switch":[59],"to":[60,89,124,141,156,178],"some":[65],"point":[66],"transferring":[68],"values":[70],"architectural":[73],"variables,":[74],"thus":[75,82,101],"speeding":[76],"up":[77],"\u201cwarm-up\u201d":[79],"phase.":[80],"However,":[81],"far":[83],"limited":[88],"processor":[90],"designs":[91],"as":[92],"other":[93],"SoC":[94],"components":[95],"lack":[96],"high-level":[97],"models":[99,118,167],"notion":[103],"instructions.":[105],"Even":[106],"for":[107,137,168],"significant":[109],"manual":[110],"effort":[111],"is":[112,149],"required":[113],"in":[114],"connecting":[115],"two":[117],"constructing":[120],"necessary":[122],"controller":[123],"synchronize/check/swap":[125],"between":[126,160],"them.":[127],"This":[128],"paper":[129],"leverages":[130],"recently":[132],"proposed":[133],"Instruction-level":[134],"Abstractions":[135],"(ILAs)":[136],"generalizing":[138],"accelerators.":[142,172],"we":[144],"use":[145],"refinement-map":[147],"that":[148],"part":[150],"ILA":[153,162],"verification":[154],"methodology":[155],"automate":[157],"connection":[159],"both":[169],"processors":[170],"We":[173],"provide":[174],"seven":[175],"case":[176],"studies":[177],"demonstrate":[179],"practical":[181],"applicability":[182],"our":[184],"methodology.":[185]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}