{"id":"https://openalex.org/W4212928402","doi":"https://doi.org/10.1109/asp-dac52403.2022.9712518","title":"Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques","display_name":"Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques","publication_year":2022,"publication_date":"2022-01-17","ids":{"openalex":"https://openalex.org/W4212928402","doi":"https://doi.org/10.1109/asp-dac52403.2022.9712518"},"language":"en","primary_location":{"id":"doi:10.1109/asp-dac52403.2022.9712518","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asp-dac52403.2022.9712518","pdf_url":null,"source":{"id":"https://openalex.org/S4363608500","display_name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003139759","display_name":"Sajjad Parvin","orcid":"https://orcid.org/0000-0002-3069-8791"},"institutions":[{"id":"https://openalex.org/I180437899","display_name":"University of Bremen","ror":"https://ror.org/04ers2y35","country_code":"DE","type":"education","lineage":["https://openalex.org/I180437899"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Sajjad Parvin","raw_affiliation_strings":["Institute of Computer Science, University of Bremen,Germany","Institute of Computer Science, University of Bremen, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Science, University of Bremen,Germany","institution_ids":["https://openalex.org/I180437899"]},{"raw_affiliation_string":"Institute of Computer Science, University of Bremen, Germany","institution_ids":["https://openalex.org/I180437899"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015270861","display_name":"Thilo Krachenfels","orcid":"https://orcid.org/0000-0002-8569-2020"},"institutions":[{"id":"https://openalex.org/I4577782","display_name":"Technische Universit\u00e4t Berlin","ror":"https://ror.org/03v4gjf40","country_code":"DE","type":"education","lineage":["https://openalex.org/I4577782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Thilo Krachenfels","raw_affiliation_strings":["Chair of Security in Telecommunications, Technische Universität Berlin,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chair of Security in Telecommunications, Technische Universität Berlin,Germany","institution_ids":["https://openalex.org/I4577782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002624062","display_name":"Shahin Tajik","orcid":"https://orcid.org/0000-0003-3752-2358"},"institutions":[{"id":"https://openalex.org/I107077323","display_name":"Worcester Polytechnic Institute","ror":"https://ror.org/05ejpqr48","country_code":"US","type":"education","lineage":["https://openalex.org/I107077323"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shahin Tajik","raw_affiliation_strings":["Worcester Polytechnique Institute,Department of Electrical and Computer Engineering,USA","Department of Electrical and Computer Engineering, Worcester Polytechnique Institute, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Worcester Polytechnique Institute,Department of Electrical and Computer Engineering,USA","institution_ids":["https://openalex.org/I107077323"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Worcester Polytechnique Institute, USA","institution_ids":["https://openalex.org/I107077323"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102712144","display_name":"Jean-Pierre Seifert","orcid":"https://orcid.org/0000-0001-5725-4667"},"institutions":[{"id":"https://openalex.org/I4577782","display_name":"Technische Universit\u00e4t Berlin","ror":"https://ror.org/03v4gjf40","country_code":"DE","type":"education","lineage":["https://openalex.org/I4577782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jean-Pierre Seifert","raw_affiliation_strings":["Chair of Security in Telecommunications, Technische Universität Berlin,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chair of Security in Telecommunications, Technische Universität Berlin,Germany","institution_ids":["https://openalex.org/I4577782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056538809","display_name":"Frank Sill Torres","orcid":"https://orcid.org/0000-0002-4028-455X"},"institutions":[{"id":"https://openalex.org/I2898391981","display_name":"Deutsches Zentrum f\u00fcr Luft- und Raumfahrt e. V. (DLR)","ror":"https://ror.org/04bwf3e34","country_code":"DE","type":"facility","lineage":["https://openalex.org/I1305996414","https://openalex.org/I2898391981"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Frank Sill Torres","raw_affiliation_strings":["Institute for the Protection of Maritime Infrastructures, German Aerospace Center,Germany","Institute for the Protection of Maritime Infrastructures, German Aerospace Center, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for the Protection of Maritime Infrastructures, German Aerospace Center,Germany","institution_ids":["https://openalex.org/I2898391981"]},{"raw_affiliation_string":"Institute for the Protection of Maritime Infrastructures, German Aerospace Center, Germany","institution_ids":["https://openalex.org/I2898391981"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071742136","display_name":"Rolf Drechsler","orcid":"https://orcid.org/0000-0002-9872-1740"},"institutions":[{"id":"https://openalex.org/I33256026","display_name":"German Research Centre for Artificial Intelligence","ror":"https://ror.org/01ayc5b57","country_code":"DE","type":"funder","lineage":["https://openalex.org/I33256026"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Rolf Drechsler","raw_affiliation_strings":["Cyber-Physical Systems, DFKI GmbH,Germany","Cyber-Physical Systems, DFKI GmbH, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cyber-Physical Systems, DFKI GmbH,Germany","institution_ids":["https://openalex.org/I33256026"]},{"raw_affiliation_string":"Cyber-Physical Systems, DFKI GmbH, Germany","institution_ids":["https://openalex.org/I33256026"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.1457,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.95834558,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":95,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"429","last_page":"435"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12495","display_name":"Electrostatic Discharge in Electronics","score":0.9904999732971191,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6493100523948669},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6473404765129089},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5456661581993103},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5377277731895447},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5330668091773987},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.5289608836174011},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4905228018760681},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.488605797290802},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.46621400117874146},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.46217554807662964},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.44230902194976807},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.42701002955436707},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4260694980621338},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22397589683532715},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21066829562187195},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2048344910144806},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.2026730179786682},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16911205649375916},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12579622864723206}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6493100523948669},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6473404765129089},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5456661581993103},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5377277731895447},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5330668091773987},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.5289608836174011},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4905228018760681},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.488605797290802},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.46621400117874146},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.46217554807662964},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.44230902194976807},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.42701002955436707},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4260694980621338},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22397589683532715},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21066829562187195},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2048344910144806},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.2026730179786682},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16911205649375916},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12579622864723206},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/asp-dac52403.2022.9712518","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asp-dac52403.2022.9712518","pdf_url":null,"source":{"id":"https://openalex.org/S4363608500","display_name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},{"id":"pmh:oai:elib.dlr.de:190209","is_oa":false,"landing_page_url":"https://ieeexplore.ieee.org/abstract/document/9712518","pdf_url":null,"source":{"id":"https://openalex.org/S4377196266","display_name":"elib (German Aerospace Center)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2898391981","host_organization_name":"Deutsches Zentrum f\u00fcr Luft- und Raumfahrt e. V. (DLR)","host_organization_lineage":["https://openalex.org/I2898391981"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Konferenzbeitrag"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G6052077811","display_name":null,"funder_award_id":"2253-439918011","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"}],"funders":[{"id":"https://openalex.org/F4320320879","display_name":"Deutsche Forschungsgemeinschaft","ror":"https://ror.org/018mejw64"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W2120000030","https://openalex.org/W2127282927","https://openalex.org/W2153843906","https://openalex.org/W2156131510","https://openalex.org/W2461274718","https://openalex.org/W2474475575","https://openalex.org/W2479752304","https://openalex.org/W2520850232","https://openalex.org/W2535614716","https://openalex.org/W2609526441","https://openalex.org/W2895166373","https://openalex.org/W2896027805","https://openalex.org/W2924330928","https://openalex.org/W2951822201","https://openalex.org/W3115465877","https://openalex.org/W3152552921","https://openalex.org/W3159130408","https://openalex.org/W3177097405","https://openalex.org/W4212961314","https://openalex.org/W6790418948"],"related_works":["https://openalex.org/W2017528947","https://openalex.org/W2789662562","https://openalex.org/W2021357106","https://openalex.org/W2082591327","https://openalex.org/W2167525841","https://openalex.org/W1529529399","https://openalex.org/W2373127312","https://openalex.org/W2356714888","https://openalex.org/W2063209251","https://openalex.org/W2965922527"],"abstract_inverted_index":{"Laser-assisted":[0],"side-channel":[1],"analysis":[2],"techniques,":[3],"such":[4],"as":[5],"optical":[6,111],"probing":[7],"(OP),":[8],"have":[9,23],"been":[10,24],"shown":[11],"to":[12,17,76,108],"pose":[13],"a":[14,39,57],"severe":[15],"threat":[16],"secure":[18],"hardware.":[19],"While":[20],"several":[21,87],"countermeasures":[22],"proposed":[25,122],"in":[26,41,94],"the":[27,42,60,110,115,130,135],"literature,":[28],"they":[29],"can":[30],"either":[31],"be":[32],"bypassed":[33],"by":[34],"an":[35],"attacker":[36],"or":[37],"require":[38],"modification":[40],"transistor's":[43],"fabrication":[44],"process,":[45],"which":[46],"is":[47,140],"costly":[48],"and":[49,73,90,98,126],"complex.":[50],"In":[51,102],"this":[52,103],"work,":[53],"firstly,":[54],"we":[55,68,85,105],"propose":[56,69],"formulation":[58],"for":[59],"caliber":[61],"of":[62,96,134],"reflected":[63,136],"light":[64,137],"from":[65,138],"OP.":[66],"Secondly,":[67],"circuit":[70,91,123],"design":[71,92,124],"techniques":[72,93,125],"logic":[74,88,117,128],"styles":[75],"alleviate":[77],"OP":[78,99,139],"attacks":[79],"based":[80],"on":[81],"our":[82,121],"formulation.":[83],"Finally,":[84],"compare":[86,109],"families":[89],"terms":[95],"performance":[97],"security":[100],"merits.":[101],"regard,":[104],"perform":[106],"simulations":[107],"beam":[112],"interaction":[113],"between":[114],"different":[116],"gates.":[118],"By":[119],"utilizing":[120],"dual-rail":[127],"(DRL),":[129],"signal-to-noise":[131],"ratio":[132],"(SNR)":[133],"reduced":[141],"significantly.":[142]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":6}],"updated_date":"2026-07-02T09:51:11.867554","created_date":"2025-10-10T00:00:00"}