{"id":"https://openalex.org/W3013288889","doi":"https://doi.org/10.1109/asp-dac47756.2020.9045729","title":"SP&amp;R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm","display_name":"SP&amp;R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm","publication_year":2020,"publication_date":"2020-01-01","ids":{"openalex":"https://openalex.org/W3013288889","doi":"https://doi.org/10.1109/asp-dac47756.2020.9045729","mag":"3013288889"},"language":"en","primary_location":{"id":"doi:10.1109/asp-dac47756.2020.9045729","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asp-dac47756.2020.9045729","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020675859","display_name":"Dong-Won Park","orcid":"https://orcid.org/0009-0004-9370-4820"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Dongwon Park","raw_affiliation_strings":["Electrical and Computer Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020579449","display_name":"Daeyeal Lee","orcid":"https://orcid.org/0000-0003-0778-0110"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Daeyeal Lee","raw_affiliation_strings":["Electrical and Computer Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008689590","display_name":"Ilgweon Kang","orcid":"https://orcid.org/0000-0003-3842-5613"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ilgweon Kang","raw_affiliation_strings":["Cadence Design Systems, Inc., San Jose, California"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Inc., San Jose, California","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081085178","display_name":"Sicun Gao","orcid":"https://orcid.org/0000-0003-2524-4960"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sicun Gao","raw_affiliation_strings":["Computer Science and Engineering, UC San Diego, La Jolla, California"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science and Engineering, UC San Diego, La Jolla, California","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061781904","display_name":"Bill Lin","orcid":"https://orcid.org/0000-0003-0965-7247"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Bill Lin","raw_affiliation_strings":["Electrical and Computer Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039615312","display_name":"Chung\u2010Kuan Cheng","orcid":"https://orcid.org/0000-0002-9865-8390"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chung-Kuan Cheng","raw_affiliation_strings":["Computer Science and Engineering, UC San Diego, La Jolla, California"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science and Engineering, UC San Diego, La Jolla, California","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.1104,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.76976306,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"345","last_page":"350"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.8132132291793823},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6810913681983948},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6706181764602661},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.6684972047805786},{"id":"https://openalex.org/keywords/modulo","display_name":"Modulo","score":0.6499555706977844},{"id":"https://openalex.org/keywords/satisfiability-modulo-theories","display_name":"Satisfiability modulo theories","score":0.4980502128601074},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4646107256412506},{"id":"https://openalex.org/keywords/boolean-satisfiability-problem","display_name":"Boolean satisfiability problem","score":0.46123552322387695},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4428390860557556},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4136890172958374},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.41296079754829407},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.38496091961860657},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.37136903405189514},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.35286617279052734},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.27159303426742554},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.24916183948516846},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.22300320863723755},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.19330421090126038},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.11767536401748657},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.11496403813362122}],"concepts":[{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.8132132291793823},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6810913681983948},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6706181764602661},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.6684972047805786},{"id":"https://openalex.org/C54732982","wikidata":"https://www.wikidata.org/wiki/Q1415345","display_name":"Modulo","level":2,"score":0.6499555706977844},{"id":"https://openalex.org/C164155591","wikidata":"https://www.wikidata.org/wiki/Q2067766","display_name":"Satisfiability modulo theories","level":2,"score":0.4980502128601074},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4646107256412506},{"id":"https://openalex.org/C6943359","wikidata":"https://www.wikidata.org/wiki/Q875276","display_name":"Boolean satisfiability problem","level":2,"score":0.46123552322387695},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4428390860557556},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4136890172958374},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.41296079754829407},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.38496091961860657},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.37136903405189514},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35286617279052734},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.27159303426742554},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.24916183948516846},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.22300320863723755},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.19330421090126038},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.11767536401748657},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.11496403813362122},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asp-dac47756.2020.9045729","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asp-dac47756.2020.9045729","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6100000143051147,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W602497127","https://openalex.org/W1022177737","https://openalex.org/W1481397690","https://openalex.org/W2009815534","https://openalex.org/W2040894443","https://openalex.org/W2054095206","https://openalex.org/W2061080621","https://openalex.org/W2063553865","https://openalex.org/W2137174619","https://openalex.org/W2138876803","https://openalex.org/W2142968870","https://openalex.org/W2588781650","https://openalex.org/W2605337839","https://openalex.org/W2626325543","https://openalex.org/W2772189580","https://openalex.org/W2772390328","https://openalex.org/W2773750423","https://openalex.org/W2808428854","https://openalex.org/W2810945905","https://openalex.org/W2886805397","https://openalex.org/W2936007546","https://openalex.org/W2946290290","https://openalex.org/W4230970194","https://openalex.org/W4245622810"],"related_works":["https://openalex.org/W1945774704","https://openalex.org/W1505872263","https://openalex.org/W4241145878","https://openalex.org/W2345938231","https://openalex.org/W2141151670","https://openalex.org/W2956134060","https://openalex.org/W4285064683","https://openalex.org/W2963523951","https://openalex.org/W2171793444","https://openalex.org/W4308390421"],"abstract_inverted_index":{"Standard":[0],"cell":[1,57,115,138,174],"synthesis":[2],"requires":[3],"careful":[4],"engineering":[5],"approaches":[6,64],"to":[7,26,45,134,167],"ensure":[8],"routability":[9],"across":[10],"various":[11],"digital":[12],"IC":[13],"designs":[14,175],"since":[15],"physical":[16],"design":[17,31,42],"(PD)":[18],"for":[19,53,68,95],"sub-7nm":[20,177],"technology":[21,49,178],"nodes":[22],"demands":[23],"holistic":[24],"efforts":[25],"address":[27],"urgent":[28],"and":[29,39,60,72,107],"nontrivial":[30],"challenges.":[32],"The":[33,117],"smaller":[34],"number":[35],"of":[36,78,128,142,157,163],"routing":[37],"tracks":[38],"more":[40],"complex":[41],"rules":[43],"due":[44],"the":[46,79,121,129,168],"sophisticated":[47],"multi-patterning":[48],"make":[50],"place-and-route":[51],"(P&R)":[52],"designing":[54,96],"a":[55,87],"standard":[56,97,137,173],"extremely":[58],"hard":[59],"time-consuming.":[61],"Many":[62],"conventional":[63],"have":[65],"been":[66],"suggested":[67],"improving":[69],"transistor-level":[70],"P&R":[71,94],"pin":[73,113],"accessibility,":[74],"nonetheless":[75],"insufficient":[76],"because":[77],"heuristic/divide-and-conquer":[80],"manners.":[81],"In":[82],"this":[83],"paper,":[84],"we":[85],"propose":[86],"novel":[88],"framework,":[89],"SP&R,":[90],"which":[91],"simultaneously":[92],"solves":[93],"cell's":[98],"layout":[99,139],"without":[100],"deploying":[101],"any":[102],"sequential":[103,169],"procedures":[104],"(between":[105],"place":[106],"route":[108],"steps)":[109],"by":[110,140],"using":[111],"dynamic":[112],"allocation-based":[114],"synthesis.":[116],"proposed":[118],"SP&R":[119,153],"utilizes":[120],"Optimization":[122],"Modulo":[123],"Theories":[124],"(OMT),":[125],"an":[126],"extension":[127],"Satisfiability":[130],"modulo":[131],"theories":[132],"(SMT),":[133],"obtain":[135],"optimal":[136],"virtue":[141],"SAT":[143],"(Boolean":[144],"Satisfiability)-based":[145],"fast":[146],"reasoning":[147],"ability.":[148],"We":[149],"validate":[150],"that":[151],"our":[152],"framework":[154],"achieves":[155],"10.5%":[156],"reduction":[158],"on":[159],"average":[160],"in":[161],"terms":[162],"metal":[164],"length":[165],"compared":[166],"approach,":[170],"through":[171],"practical":[172],"targeting":[176],"nodes.":[179]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
