{"id":"https://openalex.org/W4391183682","doi":"https://doi.org/10.1109/asicon58565.2023.10396657","title":"An Enhanced Packing Algorithm for FPGA Architectures without Local Crossbar","display_name":"An Enhanced Packing Algorithm for FPGA Architectures without Local Crossbar","publication_year":2023,"publication_date":"2023-10-24","ids":{"openalex":"https://openalex.org/W4391183682","doi":"https://doi.org/10.1109/asicon58565.2023.10396657"},"language":"en","primary_location":{"id":"doi:10.1109/asicon58565.2023.10396657","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/asicon58565.2023.10396657","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102873064","display_name":"Yuanqi Wang","orcid":"https://orcid.org/0000-0003-3408-302X"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Yuanqi Wang","raw_affiliation_strings":["Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075312901","display_name":"Kaichuang Shi","orcid":"https://orcid.org/0000-0002-6343-2930"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kaichuang Shi","raw_affiliation_strings":["Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002732486","display_name":"Lingli Wang","orcid":"https://orcid.org/0000-0002-0579-3527"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lingli Wang","raw_affiliation_strings":["Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5102873064"],"corresponding_institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18368949,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.8040031790733337},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7269080877304077},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6482388973236084},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.6049904823303223},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5819136500358582},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5762683749198914},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5745947957038879},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5660114884376526},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5547870397567749},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.4788810610771179},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.45734214782714844},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4115343987941742},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3438923954963684},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.14716836810112},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12558063864707947},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07280898094177246}],"concepts":[{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.8040031790733337},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7269080877304077},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6482388973236084},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.6049904823303223},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5819136500358582},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5762683749198914},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5745947957038879},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5660114884376526},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5547870397567749},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.4788810610771179},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.45734214782714844},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4115343987941742},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3438923954963684},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.14716836810112},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12558063864707947},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07280898094177246},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon58565.2023.10396657","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/asicon58565.2023.10396657","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1966460368","https://openalex.org/W2072249022","https://openalex.org/W2155316178","https://openalex.org/W2918037051","https://openalex.org/W3206505512","https://openalex.org/W3214834048","https://openalex.org/W4220769335"],"related_works":["https://openalex.org/W2145932742","https://openalex.org/W2554791727","https://openalex.org/W1874409533","https://openalex.org/W1981395029","https://openalex.org/W2108083791","https://openalex.org/W4297664933","https://openalex.org/W2145017421","https://openalex.org/W2387264083","https://openalex.org/W2604877941","https://openalex.org/W2390885485"],"abstract_inverted_index":{"In":[0],"the":[1,16,26,46,59,78,93,101,106,116,125,133],"EDA":[2],"process":[3,28],"of":[4,29,96,105,119],"FPGA,":[5],"VTR":[6],"(Verilog-to-Routing)":[7],"is":[8,25,36,49],"a":[9,37,85],"commonly":[10],"used":[11],"open-source":[12],"CAD":[13],"tool":[14],"in":[15,34,58,64,69,81,88],"academic":[17],"community,":[18],"and":[19,23,99,124],"VPR":[20,35,82],"(Versatile":[21],"Place":[22],"Route)":[24],"back-end":[27],"VTR.":[30],"The":[31,108],"packing":[32,47,79,134],"algorithm":[33,80,135],"seed-based":[38],"architecture-aware":[39],"algorithm,":[40],"which":[41,62],"has":[42],"strong":[43],"versatility.":[44],"However,":[45],"density":[48],"low":[50],"for":[51],"CLB":[52,98],"architectures":[53],"without":[54],"local":[55],"crossbar":[56,87],"interconnect":[57],"commercial":[60],"FPGAs,":[61],"results":[63],"long":[65],"critical":[66,102,127],"path":[67,103,128],"delays":[68],"circuits.":[70],"To":[71],"solve":[72],"this":[73,75],"problem,":[74],"paper":[76],"optimizes":[77],"by":[83,122,130],"adding":[84],"virtual":[86],"CLB,":[89],"aiming":[90],"to":[91],"improve":[92],"internal":[94],"utilization":[95],"each":[97],"decrease":[100],"delay":[104,129],"circuit.":[107],"experimental":[109],"result":[110],"shows":[111],"that":[112],"it":[113],"can":[114],"reduce":[115],"average":[117,126],"number":[118],"packed":[120],"CLBs":[121],"56.51%":[123],"9.14%":[131],"after":[132],"enhancement.":[136]},"counts_by_year":[],"updated_date":"2025-12-21T23:12:01.093139","created_date":"2025-10-10T00:00:00"}
