{"id":"https://openalex.org/W4391183573","doi":"https://doi.org/10.1109/asicon58565.2023.10396616","title":"A Vernier Time-to-Digital Converter with 1.5ps Resolution for an All-Digital Phase Locked Loop in 28nm CMOS","display_name":"A Vernier Time-to-Digital Converter with 1.5ps Resolution for an All-Digital Phase Locked Loop in 28nm CMOS","publication_year":2023,"publication_date":"2023-10-24","ids":{"openalex":"https://openalex.org/W4391183573","doi":"https://doi.org/10.1109/asicon58565.2023.10396616"},"language":"en","primary_location":{"id":"doi:10.1109/asicon58565.2023.10396616","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/asicon58565.2023.10396616","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111117786","display_name":"Peifang Wu","orcid":"https://orcid.org/0009-0003-5985-2398"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Peifang Wu","raw_affiliation_strings":["Fudan University,State Key Laboratory of Integrated Chip and Systems,Shanghai,China","State Key Laboratory of Integrated Chip and Systems, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Laboratory of Integrated Chip and Systems,Shanghai,China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of Integrated Chip and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100351119","display_name":"Yan Liu","orcid":"https://orcid.org/0000-0002-8645-5123"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yan Liu","raw_affiliation_strings":["Fudan University,State Key Laboratory of Integrated Chip and Systems,Shanghai,China","State Key Laboratory of Integrated Chip and Systems, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Laboratory of Integrated Chip and Systems,Shanghai,China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of Integrated Chip and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021368404","display_name":"Xi Feng","orcid":"https://orcid.org/0000-0003-0858-893X"},"institutions":[{"id":"https://openalex.org/I4210089056","display_name":"Beijing Microelectronics Technology Institute","ror":"https://ror.org/007y7ej30","country_code":"CN","type":"other","lineage":["https://openalex.org/I4210089056"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xi Feng","raw_affiliation_strings":["Beijing Smartchip Semiconductor Technology Co., Ltd,Beijing Smartchip Microelectronics Technology Co., Ltd,Beijing,China","Beijing Smartchip Microelectronics Technology Co., Ltd, Beijing Smartchip Semiconductor Technology Co., Ltd, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Beijing Smartchip Semiconductor Technology Co., Ltd,Beijing Smartchip Microelectronics Technology Co., Ltd,Beijing,China","institution_ids":["https://openalex.org/I4210089056"]},{"raw_affiliation_string":"Beijing Smartchip Microelectronics Technology Co., Ltd, Beijing Smartchip Semiconductor Technology Co., Ltd, Beijing, China","institution_ids":["https://openalex.org/I4210089056"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104221778","display_name":"Hao Xu","orcid":"https://orcid.org/0009-0009-6706-3704"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hao Xu","raw_affiliation_strings":["Fudan University,State Key Laboratory of Integrated Chip and Systems,Shanghai,China","State Key Laboratory of Integrated Chip and Systems, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Laboratory of Integrated Chip and Systems,Shanghai,China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of Integrated Chip and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083182163","display_name":"Na Yan","orcid":"https://orcid.org/0000-0001-7012-404X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Na Yan","raw_affiliation_strings":["Fudan University,State Key Laboratory of Integrated Chip and Systems,Shanghai,China","State Key Laboratory of Integrated Chip and Systems, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Laboratory of Integrated Chip and Systems,Shanghai,China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of Integrated Chip and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5111117786"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18341179,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vernier-scale","display_name":"Vernier scale","score":0.9407074451446533},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7468204498291016},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6983903050422668},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.6453827619552612},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"Time-to-digital converter","score":0.6300809383392334},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6033307909965515},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46325573325157166},{"id":"https://openalex.org/keywords/resolution","display_name":"Resolution (logic)","score":0.41676628589630127},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.17552870512008667},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1327577829360962},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12235340476036072},{"id":"https://openalex.org/keywords/optics","display_name":"Optics","score":0.09018802642822266},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.08937570452690125},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.0874895453453064},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08742046356201172}],"concepts":[{"id":"https://openalex.org/C69710193","wikidata":"https://www.wikidata.org/wiki/Q14946576","display_name":"Vernier scale","level":2,"score":0.9407074451446533},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7468204498291016},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6983903050422668},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.6453827619552612},{"id":"https://openalex.org/C99594498","wikidata":"https://www.wikidata.org/wiki/Q2434524","display_name":"Time-to-digital converter","level":4,"score":0.6300809383392334},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6033307909965515},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46325573325157166},{"id":"https://openalex.org/C138268822","wikidata":"https://www.wikidata.org/wiki/Q1051925","display_name":"Resolution (logic)","level":2,"score":0.41676628589630127},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.17552870512008667},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1327577829360962},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12235340476036072},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.09018802642822266},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08937570452690125},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0874895453453064},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08742046356201172},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon58565.2023.10396616","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/asicon58565.2023.10396616","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.75,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2062952706","https://openalex.org/W2075169931","https://openalex.org/W2128282260","https://openalex.org/W2163903773","https://openalex.org/W2168322829","https://openalex.org/W2479854745","https://openalex.org/W2503049326","https://openalex.org/W2782546029"],"related_works":["https://openalex.org/W3158414702","https://openalex.org/W4389545333","https://openalex.org/W2296652335","https://openalex.org/W2182982459","https://openalex.org/W2112856903","https://openalex.org/W2120912680","https://openalex.org/W2541226935","https://openalex.org/W3022509112","https://openalex.org/W2547517791","https://openalex.org/W2126265853"],"abstract_inverted_index":{"A":[0],"vernier":[1],"delay":[2,16,20],"line":[3,17],"based":[4],"time-to-digital":[5],"converter(TDC)":[6],"with":[7,18,74],"high":[8],"resolution":[9,71],"is":[10,22,35,57],"presented":[11],"in":[12,59],"this":[13],"paper.":[14],"Vernier":[15],"different":[19],"time":[21,43],"generated":[23],"by":[24],"changing":[25],"the":[26,41,48,76],"buffer\u2019s":[27],"output":[28],"capacitance,":[29],"sense":[30],"amplifier":[31],"flip":[32],"flop":[33],"(SAFF)":[34],"used":[36],"as":[37],"arbitrator":[38],"to":[39,51],"quantize":[40],"input":[42],"interval":[44],"and":[45,78],"decoder":[46],"converts":[47],"thermometer":[49],"code":[50],"binary":[52],"code.":[53],"The":[54],"proposed":[55],"TDC":[56],"implemented":[58],"28nm":[60],"CMOS.":[61],"Post":[62],"simulation":[63],"results":[64],"show":[65],"that":[66],"it":[67],"can":[68],"achieve":[69],"a":[70],"about":[72],"1.5ps":[73],"both":[75],"INL":[77],"DNL":[79],"less":[80],"than":[81],"one":[82],"LSB.":[83]},"counts_by_year":[],"updated_date":"2025-12-25T23:11:45.687758","created_date":"2025-10-10T00:00:00"}
