{"id":"https://openalex.org/W4391183607","doi":"https://doi.org/10.1109/asicon58565.2023.10396595","title":"A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm CMOS Technology","display_name":"A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm CMOS Technology","publication_year":2023,"publication_date":"2023-10-24","ids":{"openalex":"https://openalex.org/W4391183607","doi":"https://doi.org/10.1109/asicon58565.2023.10396595"},"language":"en","primary_location":{"id":"doi:10.1109/asicon58565.2023.10396595","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/asicon58565.2023.10396595","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060201341","display_name":"Bingrong Lyu","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Bingrong Lyu","raw_affiliation_strings":["Fudan University,State Key Lab. of ASIC &amp; System,Shanghai,China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Lab. of ASIC &amp; System,Shanghai,China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025053306","display_name":"Fan Ye","orcid":"https://orcid.org/0000-0002-1089-1498"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Fan Ye","raw_affiliation_strings":["Fudan University,State Key Lab. of ASIC &amp; System,Shanghai,China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Lab. of ASIC &amp; System,Shanghai,China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016448886","display_name":"Junyan Ren","orcid":"https://orcid.org/0000-0002-7799-6251"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Junyan Ren","raw_affiliation_strings":["Fudan University,State Key Lab. of ASIC &amp; System,Shanghai,China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Lab. of ASIC &amp; System,Shanghai,China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5060201341"],"corresponding_institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18361549,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7856096029281616},{"id":"https://openalex.org/keywords/transmitter","display_name":"Transmitter","score":0.7682842016220093},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5903586149215698},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.5681528449058533},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5164608955383301},{"id":"https://openalex.org/keywords/output-impedance","display_name":"Output impedance","score":0.43363386392593384},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4161016047000885},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.3908601999282837},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3680613934993744},{"id":"https://openalex.org/keywords/electrical-impedance","display_name":"Electrical impedance","score":0.31260746717453003},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.29181069135665894}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7856096029281616},{"id":"https://openalex.org/C47798520","wikidata":"https://www.wikidata.org/wiki/Q190157","display_name":"Transmitter","level":3,"score":0.7682842016220093},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5903586149215698},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.5681528449058533},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5164608955383301},{"id":"https://openalex.org/C58112919","wikidata":"https://www.wikidata.org/wiki/Q631203","display_name":"Output impedance","level":3,"score":0.43363386392593384},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4161016047000885},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.3908601999282837},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3680613934993744},{"id":"https://openalex.org/C17829176","wikidata":"https://www.wikidata.org/wiki/Q179043","display_name":"Electrical impedance","level":2,"score":0.31260746717453003},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.29181069135665894}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon58565.2023.10396595","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/asicon58565.2023.10396595","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8299999833106995,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320337504","display_name":"Research and Development","ror":"https://ror.org/027s68j25"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1483685374","https://openalex.org/W2058752027","https://openalex.org/W2142626251","https://openalex.org/W2291926886","https://openalex.org/W2907379053","https://openalex.org/W4310502234"],"related_works":["https://openalex.org/W2355663289","https://openalex.org/W4297786912","https://openalex.org/W2572422521","https://openalex.org/W2356432821","https://openalex.org/W2026961927","https://openalex.org/W2135402579","https://openalex.org/W4386577649","https://openalex.org/W2345433773","https://openalex.org/W4243306918","https://openalex.org/W2771465347"],"abstract_inverted_index":{"A":[0],"6-Gb/s":[1,94],"half":[2,34],"rate":[3,35],"current":[4],"mode":[5],"logic":[6],"(CML)":[7],"transmitter":[8,92,107],"has":[9],"been":[10],"designed":[11],"in":[12,87],"TSMC":[13],"28nm":[14,88],"CMOS":[15,89],"technology,":[16,90],"which":[17],"employs":[18],"a":[19,38,119],"3-tap":[20],"3-bit":[21],"feed":[22],"forward":[23],"equalizer":[24],"(FFE),":[25],"an":[26],"analog":[27],"duty":[28,74],"cycle":[29,75],"correction":[30],"module":[31,43,71],"(DCC)":[32],"for":[33,44,56],"clock":[36,109],"and":[37,77,117],"5-bit":[39],"output":[40],"impedance":[41,83],"calibration":[42],"100-ohm":[45],"differential":[46],"load.":[47],"Post-layout":[48],"simulation":[49],"indicates":[50],"that":[51],"the":[52,81,91],"FFE":[53],"could":[54,72],"compensate":[55],"up":[57],"to":[58],"4.7dB":[59,101],"channel":[60,102],"loss":[61],"at":[62,104],"3GHz":[63],"while":[64],"maintaining":[65],"410mVpp":[66],"eye":[67],"height.":[68],"The":[69,106],"DCC":[70],"corrects\u00b130%":[73],"mismatch":[76],"max":[78],"deviation":[79],"of":[80,122],"calibrated":[82],"is":[84],"2.7%.":[85],"Implemented":[86],"delivers":[93],"data":[95],"(2<sup":[96],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[97],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">15</sup>-1":[98],"PRBS)":[99],"with":[100],"attenuation":[103],"3GHz.":[105],"(excluding":[108],"generating":[110],"PLL)":[111],"consumes":[112],"27.67mA":[113],"from":[114],"0.9V":[115],"supply":[116],"occupies":[118],"die":[120],"area":[121],"214\u03bcm":[123],"*":[124],"108\u03bcm.":[125]},"counts_by_year":[],"updated_date":"2025-12-23T23:11:35.936235","created_date":"2025-10-10T00:00:00"}
