{"id":"https://openalex.org/W4391183659","doi":"https://doi.org/10.1109/asicon58565.2023.10396594","title":"A Low Jitter Current-Mode Multiplying Delay-Locked Loop Applied to High-Precision TDC","display_name":"A Low Jitter Current-Mode Multiplying Delay-Locked Loop Applied to High-Precision TDC","publication_year":2023,"publication_date":"2023-10-24","ids":{"openalex":"https://openalex.org/W4391183659","doi":"https://doi.org/10.1109/asicon58565.2023.10396594"},"language":"en","primary_location":{"id":"doi:10.1109/asicon58565.2023.10396594","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/asicon58565.2023.10396594","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108613991","display_name":"Jin Sun","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]},{"id":"https://openalex.org/I4210147760","display_name":"Wuhu Institute of Technology","ror":"https://ror.org/055hnk386","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210147760"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jin Sun","raw_affiliation_strings":["Xidian University,College of Microelectronics,Xi'an,China","College of Microelectronics, Xidian University, Xi'an, China","Wuhu Research Institute, Xidian University, Wuhu, China"],"affiliations":[{"raw_affiliation_string":"Xidian University,College of Microelectronics,Xi'an,China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"College of Microelectronics, Xidian University, Xi'an, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"Wuhu Research Institute, Xidian University, Wuhu, China","institution_ids":["https://openalex.org/I4210147760","https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081006428","display_name":"Jiahao Hu","orcid":"https://orcid.org/0000-0001-5835-1012"},"institutions":[{"id":"https://openalex.org/I4210147760","display_name":"Wuhu Institute of Technology","ror":"https://ror.org/055hnk386","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210147760"]},{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jiahao Hu","raw_affiliation_strings":["Xidian University,College of Microelectronics,Xi'an,China","College of Microelectronics, Xidian University, Xi'an, China","Wuhu Research Institute, Xidian University, Wuhu, China"],"affiliations":[{"raw_affiliation_string":"Xidian University,College of Microelectronics,Xi'an,China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"College of Microelectronics, Xidian University, Xi'an, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"Wuhu Research Institute, Xidian University, Wuhu, China","institution_ids":["https://openalex.org/I4210147760","https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101025708","display_name":"Ziqi Song","orcid":"https://orcid.org/0009-0005-0837-7771"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]},{"id":"https://openalex.org/I4210147760","display_name":"Wuhu Institute of Technology","ror":"https://ror.org/055hnk386","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210147760"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ziqi Song","raw_affiliation_strings":["Xidian University,Wuhu Research Institute,Wuhu,China","Wuhu Research Institute, Xidian University, Wuhu, China"],"affiliations":[{"raw_affiliation_string":"Xidian University,Wuhu Research Institute,Wuhu,China","institution_ids":["https://openalex.org/I4210147760"]},{"raw_affiliation_string":"Wuhu Research Institute, Xidian University, Wuhu, China","institution_ids":["https://openalex.org/I4210147760","https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100404162","display_name":"Qing Li","orcid":"https://orcid.org/0000-0003-1433-328X"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]},{"id":"https://openalex.org/I4210147760","display_name":"Wuhu Institute of Technology","ror":"https://ror.org/055hnk386","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210147760"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qing Li","raw_affiliation_strings":["Xidian University,Wuhu Research Institute,Wuhu,China","Wuhu Research Institute, Xidian University, Wuhu, China"],"affiliations":[{"raw_affiliation_string":"Xidian University,Wuhu Research Institute,Wuhu,China","institution_ids":["https://openalex.org/I4210147760"]},{"raw_affiliation_string":"Wuhu Research Institute, Xidian University, Wuhu, China","institution_ids":["https://openalex.org/I4210147760","https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110893787","display_name":"Dian He","orcid":null},"institutions":[{"id":"https://openalex.org/I4210147760","display_name":"Wuhu Institute of Technology","ror":"https://ror.org/055hnk386","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210147760"]},{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dian He","raw_affiliation_strings":["Xidian University,Wuhu Research Institute,Wuhu,China","Wuhu Research Institute, Xidian University, Wuhu, China"],"affiliations":[{"raw_affiliation_string":"Xidian University,Wuhu Research Institute,Wuhu,China","institution_ids":["https://openalex.org/I4210147760"]},{"raw_affiliation_string":"Wuhu Research Institute, Xidian University, Wuhu, China","institution_ids":["https://openalex.org/I4210147760","https://openalex.org/I149594827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100532577","display_name":"Hujun Jia","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hujun Jia","raw_affiliation_strings":["Xidian University,College of Microelectronics,Xi'an,China","College of Microelectronics, Xidian University, Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Xidian University,College of Microelectronics,Xi'an,China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"College of Microelectronics, Xidian University, Xi'an, China","institution_ids":["https://openalex.org/I149594827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5108613991"],"corresponding_institution_ids":["https://openalex.org/I149594827","https://openalex.org/I4210147760"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18366483,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12216","display_name":"Network Time Synchronization Technologies","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9069820642471313},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.6155542135238647},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.569485604763031},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4896848499774933},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.4825248420238495},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.4425736963748932},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.43284469842910767},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.43105411529541016},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.41579532623291016},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.35300207138061523},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2667667269706726},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13868829607963562}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9069820642471313},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.6155542135238647},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.569485604763031},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4896848499774933},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.4825248420238495},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.4425736963748932},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.43284469842910767},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.43105411529541016},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.41579532623291016},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.35300207138061523},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2667667269706726},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13868829607963562},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon58565.2023.10396594","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/asicon58565.2023.10396594","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1970092416","https://openalex.org/W2291605840","https://openalex.org/W2600277699","https://openalex.org/W2736058244","https://openalex.org/W2980281185","https://openalex.org/W3165875628"],"related_works":["https://openalex.org/W1994021281","https://openalex.org/W2139484866","https://openalex.org/W2113057816","https://openalex.org/W2354050524","https://openalex.org/W2083878249","https://openalex.org/W2401743820","https://openalex.org/W3177439118","https://openalex.org/W4295813049","https://openalex.org/W1550227479","https://openalex.org/W2119216036"],"abstract_inverted_index":{"This":[0,120],"paper":[1,121],"presents":[2],"a":[3,11,46,128],"low":[4],"jitter":[5,172],"multiplying":[6],"delay-locked":[7],"loop":[8,167],"(MDLL)":[9],"with":[10,24,80,130],"current-controlled":[12],"delay":[13,30,98,109],"line":[14,31],"(DL)":[15],"for":[16],"high-precision":[17,37],"time-to-digital":[18],"converter":[19],"(TDC).":[20],"A":[21],"multiphase":[22],"clock":[23],"uniform":[25],"distribution":[26],"generated":[27],"from":[28],"the":[29,36,54,68,72,87,103,108,116,145,150,159,165,170,176],"is":[32,50,83,112,153,162,168,173,185],"applied":[33],"directly":[34],"to":[35,52,66,85,114,126],"TDC.":[38,119],"To":[39],"achieve":[40],"better":[41],"performance":[42],"output":[43,132],"phase":[44,69,183],"splitting,":[45],"voltage-to-current":[47],"circuit":[48],"(VTC)":[49],"introduced":[51],"extend":[53],"locking":[55,160],"frequency":[56,60],"range":[57],"and":[58,91,175],"enhance":[59],"tuning":[61],"linearity":[62],"of":[63,118,133,138,149,179],"MDLL.":[64],"Additionally,":[65],"decrease":[67],"noise":[70,106],"in":[71,107],"locked":[73],"state,":[74],"an":[75,131,136],"improved":[76,95],"charge":[77,90],"pump":[78],"(CP)":[79],"matched":[81],"switches":[82],"utilized":[84],"improve":[86,115],"match":[88],"between":[89],"discharge":[92],"currents.":[93],"The":[94,140],"reverse":[96],"differential":[97],"cell":[99],"structure":[100],"can":[101],"suppress":[102],"common":[104],"mode":[105],"line,":[110],"which":[111],"used":[113],"resolution":[117],"uses":[122],"180nm":[123],"CMOS":[124],"technology":[125],"realize":[127],"MDLL":[129,166],"65MHz-325MHz,":[134],"occupying":[135],"area":[137],"0.084mm2.":[139],"simulation":[141],"results":[142],"show":[143],"that":[144],"total":[146],"power":[147,157],"consumption":[148],"chip":[151],"core":[152],"9.41mW@200MHz":[154],"under":[155],"1.8V":[156],"supply,":[158],"voltage":[161],"820mV":[163],"when":[164],"stable,":[169],"RMS":[171],"1.73ps@200MHz,":[174],"standard":[177],"deviation":[178],"each":[180],"45\u00b0":[181],"adjacent":[182],"interval":[184],"less":[186],"than":[187],"1.5ps.":[188]},"counts_by_year":[],"updated_date":"2025-12-19T00:32:22.182498","created_date":"2025-10-10T00:00:00"}
