{"id":"https://openalex.org/W4391183558","doi":"https://doi.org/10.1109/asicon58565.2023.10396538","title":"Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm","display_name":"Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm","publication_year":2023,"publication_date":"2023-10-24","ids":{"openalex":"https://openalex.org/W4391183558","doi":"https://doi.org/10.1109/asicon58565.2023.10396538"},"language":"en","primary_location":{"id":"doi:10.1109/asicon58565.2023.10396538","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/asicon58565.2023.10396538","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111117785","display_name":"Honghong Long","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Honghong Long","raw_affiliation_strings":["Fudan University,School of Microelectronics,Shanghai,China,200433"],"affiliations":[{"raw_affiliation_string":"Fudan University,School of Microelectronics,Shanghai,China,200433","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109351726","display_name":"Yu Bai","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153230","display_name":"Shanghai Academy of Spaceflight Technology","ror":"https://ror.org/050qhwt21","country_code":"CN","type":"government","lineage":["https://openalex.org/I2802615301","https://openalex.org/I4210153230"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yu Bai","raw_affiliation_strings":["Shanghai Academy of Spaceflight Technology,Shanghai,China,201109"],"affiliations":[{"raw_affiliation_string":"Shanghai Academy of Spaceflight Technology,Shanghai,China,201109","institution_ids":["https://openalex.org/I4210153230"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102014345","display_name":"Yanze Li","orcid":"https://orcid.org/0000-0002-9946-2349"},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yanze Li","raw_affiliation_strings":["Fudan University,School of Microelectronics,Shanghai,China,200433"],"affiliations":[{"raw_affiliation_string":"Fudan University,School of Microelectronics,Shanghai,China,200433","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002847404","display_name":"Jian Wang","orcid":"https://orcid.org/0000-0003-4361-8946"},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Wang","raw_affiliation_strings":["Fudan University,School of Microelectronics,Shanghai,China,200433"],"affiliations":[{"raw_affiliation_string":"Fudan University,School of Microelectronics,Shanghai,China,200433","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081419061","display_name":"Jinmei Lai","orcid":"https://orcid.org/0009-0003-5238-4720"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinmei Lai","raw_affiliation_strings":["Fudan University,School of Microelectronics,Shanghai,China,200433"],"affiliations":[{"raw_affiliation_string":"Fudan University,School of Microelectronics,Shanghai,China,200433","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5111117785"],"corresponding_institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4210132426"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18366038,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.8956847786903381},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.8382183313369751},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5794001817703247},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5314905643463135},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5201197862625122},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5034195780754089},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.45512741804122925},{"id":"https://openalex.org/keywords/elmore-delay","display_name":"Elmore delay","score":0.4169148802757263},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.392343670129776},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.35598477721214294},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.33909714221954346},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.2568514943122864},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2293974757194519},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20528346300125122},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1789778769016266}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.8956847786903381},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.8382183313369751},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5794001817703247},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5314905643463135},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5201197862625122},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5034195780754089},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.45512741804122925},{"id":"https://openalex.org/C84434228","wikidata":"https://www.wikidata.org/wiki/Q4531332","display_name":"Elmore delay","level":4,"score":0.4169148802757263},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.392343670129776},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.35598477721214294},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.33909714221954346},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.2568514943122864},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2293974757194519},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20528346300125122},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1789778769016266},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon58565.2023.10396538","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/asicon58565.2023.10396538","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2037524044","https://openalex.org/W2080482360","https://openalex.org/W2095258817","https://openalex.org/W2295327519","https://openalex.org/W2615966677","https://openalex.org/W2887584282","https://openalex.org/W2911751195","https://openalex.org/W4289655444"],"related_works":["https://openalex.org/W2133901311","https://openalex.org/W2087871358","https://openalex.org/W2136768364","https://openalex.org/W4386643835","https://openalex.org/W2120361800","https://openalex.org/W4256007160","https://openalex.org/W2094042791","https://openalex.org/W4205135025","https://openalex.org/W3153286430","https://openalex.org/W1535529518"],"abstract_inverted_index":{"After":[0],"studying":[1],"FPGA":[2,19],"circuit":[3],"optimization,":[4],"this":[5,133],"paper":[6,28,51,134],"improves":[7],"the":[8,14,18,23,68,102,108,116,120,124],"simulated":[9,104],"annealing":[10,105],"algorithm":[11,69,111],"to":[12,38,70,81,101,118,130,137],"floorplan":[13,141],"key":[15,35],"circuits":[16,36],"of":[17,33,123],"tile":[20],"and":[21,25,44,48,57,61,85,91,97,145],"optimize":[22],"wirelength":[24,47,84,96,144,150],"delay.":[26,49,86],"The":[27,50],"implements":[29],"a":[30,40,139],"larger":[31,41],"range":[32],"interconnect":[34],"exchange":[37],"explore":[39],"solution":[42],"space":[43],"obtain":[45,138],"better":[46,83],"also":[52],"adopts":[53],"adaptive":[54],"initial":[55],"temperature":[56],"combines":[58],"exponential":[59],"cooling":[60],"flexible":[62],"iterations":[63],"at":[64,76],"different":[65],"temperatures,":[66],"allowing":[67],"fully":[71],"utilize":[72],"time":[73,117],"for":[74,152],"optimization":[75,94,121],"an":[77],"appropriate":[78],"temperature,":[79],"aiming":[80],"achieve":[82,119],"Experimental":[87],"results":[88],"show":[89],"5.14%":[90],"1.27%":[92],"average":[93],"in":[95],"delay":[98],"respectively,":[99],"compared":[100,129],"traditional":[103,109],"algorithm.":[106,126],"Also,":[107],"SA":[110],"took":[112],"nearly":[113],"three":[114],"times":[115],"effect":[122],"new":[125],"In":[127],"addition,":[128],"previous":[131],"works,":[132],"is":[135],"able":[136],"reasonable":[140],"that":[142],"minimizes":[143],"delay,":[146],"providing":[147],"more":[148],"accurate":[149],"information":[151],"load":[153],"modeling.":[154]},"counts_by_year":[],"updated_date":"2025-12-25T23:11:45.687758","created_date":"2025-10-10T00:00:00"}
