{"id":"https://openalex.org/W4391183594","doi":"https://doi.org/10.1109/asicon58565.2023.10396489","title":"Full-custom Design of Improved Carry Adder Circuit for CLBs","display_name":"Full-custom Design of Improved Carry Adder Circuit for CLBs","publication_year":2023,"publication_date":"2023-10-24","ids":{"openalex":"https://openalex.org/W4391183594","doi":"https://doi.org/10.1109/asicon58565.2023.10396489"},"language":"en","primary_location":{"id":"doi:10.1109/asicon58565.2023.10396489","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon58565.2023.10396489","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002622136","display_name":"Mengfan Xu","orcid":"https://orcid.org/0000-0002-7966-404X"},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Mengfan Xu","raw_affiliation_strings":["Ningbo University,Faculty of Electrical Engineering and Computer Science,Ningbo,China,315211"],"affiliations":[{"raw_affiliation_string":"Ningbo University,Faculty of Electrical Engineering and Computer Science,Ningbo,China,315211","institution_ids":["https://openalex.org/I109935558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108046742","display_name":"Yuejun Zhang","orcid":"https://orcid.org/0000-0003-1132-6332"},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuejun Zhang","raw_affiliation_strings":["Ningbo University,Faculty of Electrical Engineering and Computer Science,Ningbo,China,315211"],"affiliations":[{"raw_affiliation_string":"Ningbo University,Faculty of Electrical Engineering and Computer Science,Ningbo,China,315211","institution_ids":["https://openalex.org/I109935558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074246475","display_name":"Huihong Zhang","orcid":"https://orcid.org/0000-0001-6195-4615"},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Huihong Zhang","raw_affiliation_strings":["Ningbo University,Faculty of Electrical Engineering and Computer Science,Ningbo,China,315211"],"affiliations":[{"raw_affiliation_string":"Ningbo University,Faculty of Electrical Engineering and Computer Science,Ningbo,China,315211","institution_ids":["https://openalex.org/I109935558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100960954","display_name":"Liang Wen","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Liang Wen","raw_affiliation_strings":["China Coast Guard Academy,Department of Electronic Technology,Ningbo,China,315211"],"affiliations":[{"raw_affiliation_string":"China Coast Guard Academy,Department of Electronic Technology,Ningbo,China,315211","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068300704","display_name":"Tengfei Yuan","orcid":"https://orcid.org/0000-0002-7661-5322"},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Tengfei Yuan","raw_affiliation_strings":["Ningbo University,Faculty of Electrical Engineering and Computer Science,Ningbo,China,315211"],"affiliations":[{"raw_affiliation_string":"Ningbo University,Faculty of Electrical Engineering and Computer Science,Ningbo,China,315211","institution_ids":["https://openalex.org/I109935558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106892182","display_name":"Pengjun Wang","orcid":"https://orcid.org/0000-0002-1461-3719"},"institutions":[{"id":"https://openalex.org/I146620803","display_name":"Wenzhou University","ror":"https://ror.org/020hxh324","country_code":"CN","type":"education","lineage":["https://openalex.org/I146620803"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Pengjun Wang","raw_affiliation_strings":["Wenzhou University,College of Electrical and Electronic Engineering,Wenzhou,China,325035"],"affiliations":[{"raw_affiliation_string":"Wenzhou University,College of Electrical and Electronic Engineering,Wenzhou,China,325035","institution_ids":["https://openalex.org/I146620803"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100779408","display_name":"Zhiyi Li","orcid":"https://orcid.org/0000-0002-8664-088X"},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhiyi Li","raw_affiliation_strings":["Ningbo University,Faculty of Electrical Engineering and Computer Science,Ningbo,China,315211"],"affiliations":[{"raw_affiliation_string":"Ningbo University,Faculty of Electrical Engineering and Computer Science,Ningbo,China,315211","institution_ids":["https://openalex.org/I109935558"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5002622136"],"corresponding_institution_ids":["https://openalex.org/I109935558"],"apc_list":null,"apc_paid":null,"fwci":0.4021,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.62213808,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9557681083679199},{"id":"https://openalex.org/keywords/carry","display_name":"Carry (investment)","score":0.7674797773361206},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.680458664894104},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.5830783843994141},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5638928413391113},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.5444421172142029},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5093875527381897},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4656938314437866},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45709413290023804},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.455790638923645},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.44259557127952576},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.42118537425994873},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3914954662322998},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.2692582309246063},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.22430342435836792},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2121092975139618},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.14622798562049866},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.08616843819618225}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9557681083679199},{"id":"https://openalex.org/C2776299755","wikidata":"https://www.wikidata.org/wiki/Q432449","display_name":"Carry (investment)","level":2,"score":0.7674797773361206},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.680458664894104},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.5830783843994141},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5638928413391113},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.5444421172142029},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5093875527381897},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4656938314437866},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45709413290023804},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.455790638923645},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.44259557127952576},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.42118537425994873},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3914954662322998},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.2692582309246063},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.22430342435836792},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2121092975139618},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.14622798562049866},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.08616843819618225},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon58565.2023.10396489","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon58565.2023.10396489","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6200000047683716}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320322605","display_name":"Ningbo University","ror":"https://ror.org/03et85d35"},{"id":"https://openalex.org/F4320332587","display_name":"Natural Science Foundation of Ningbo","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320336552","display_name":"Science and Technology Innovation 2025 Major Project of Ningbo","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1661984954","https://openalex.org/W2057071911","https://openalex.org/W2129394555","https://openalex.org/W2135089667","https://openalex.org/W2527231362","https://openalex.org/W2757793413","https://openalex.org/W2792876434","https://openalex.org/W2808450564","https://openalex.org/W2971830024","https://openalex.org/W2972193649","https://openalex.org/W3009607264","https://openalex.org/W3094745711","https://openalex.org/W3119693822"],"related_works":["https://openalex.org/W2364181090","https://openalex.org/W4299002946","https://openalex.org/W2950518102","https://openalex.org/W2516396101","https://openalex.org/W4308329128","https://openalex.org/W2997250644","https://openalex.org/W2556310577","https://openalex.org/W2897293593","https://openalex.org/W2889047098","https://openalex.org/W2139901278"],"abstract_inverted_index":{"As":[0],"a":[1,15,87,111],"highly":[2],"repetitive":[3],"logic":[4,9,28,101,126],"operation":[5],"unit":[6],"in":[7,73,115,133],"programmable":[8,27,74],"modules,":[10],"the":[11,22,26,65,79,83,98,104,128],"operating":[12],"speed":[13],"of":[14,25,82],"carry":[16,48,70,84,100,105,130],"adder":[17,49,54,71,106,131],"circuit":[18,34,107,132],"is":[19,94,108],"crucial":[20],"to":[21,32,63,96,124],"overall":[23],"performance":[24,59],"circuit.":[29,102],"In":[30],"order":[31],"optimize":[33,97],"propagation":[35,137],"delay":[36,138],"and":[37,57,139,144],"area":[38,140],"overhead,":[39],"this":[40,134],"paper":[41,135],"proposes":[42],"an":[43],"improved":[44],"design":[45,113],"scheme":[46],"for":[47,69],"circuits.":[50],"Firstly,":[51],"several":[52],"basic":[53],"structure":[55,93],"types":[56],"their":[58],"characteristics":[60],"are":[61],"compared":[62,123],"determine":[64],"most":[66],"suitable":[67],"architecture":[68],"circuits":[72],"modules.":[75],"Then,":[76],"based":[77],"on":[78],"carry-propagate":[80],"principle":[81],"lookahead":[85],"adder,":[86],"novel":[88],"single":[89],"MOS":[90],"transmission":[91],"gate":[92],"proposed":[95,129],"underlying":[99],"Finally,":[103],"implemented":[109],"using":[110],"full-custom":[112],"flow":[114],"TSMC":[116],"28nm":[117],"technology.":[118],"Experimental":[119],"results":[120],"show":[121],"that":[122],"existing":[125],"designs,":[127],"reduces":[136],"overhead":[141],"by":[142],"14%":[143],"26.5%":[145],"respectively.":[146]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}