{"id":"https://openalex.org/W4391183587","doi":"https://doi.org/10.1109/asicon58565.2023.10396414","title":"HierSyn: Fast Synthesis for Large Hierarchical Designs","display_name":"HierSyn: Fast Synthesis for Large Hierarchical Designs","publication_year":2023,"publication_date":"2023-10-24","ids":{"openalex":"https://openalex.org/W4391183587","doi":"https://doi.org/10.1109/asicon58565.2023.10396414"},"language":"en","primary_location":{"id":"doi:10.1109/asicon58565.2023.10396414","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon58565.2023.10396414","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061769699","display_name":"Yishan Zhang","orcid":"https://orcid.org/0009-0008-8856-0999"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Yishan Zhang","raw_affiliation_strings":["Fudan University,State-Key Lab of ASIC and System,School of Microelectronics,Shanghai,China,200433"],"affiliations":[{"raw_affiliation_string":"Fudan University,State-Key Lab of ASIC and System,School of Microelectronics,Shanghai,China,200433","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100352578","display_name":"Zhiyong Zhang","orcid":"https://orcid.org/0000-0001-7936-9510"},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhiyong Zhang","raw_affiliation_strings":["Shanghai Fudan Microelectronics Group Co., Ltd,Shanghai,China,200433"],"affiliations":[{"raw_affiliation_string":"Shanghai Fudan Microelectronics Group Co., Ltd,Shanghai,China,200433","institution_ids":["https://openalex.org/I4210132426"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102608783","display_name":"Chang Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chang Wu","raw_affiliation_strings":["Fudan University,State-Key Lab of ASIC and System,School of Microelectronics,Shanghai,China,200433"],"affiliations":[{"raw_affiliation_string":"Fudan University,State-Key Lab of ASIC and System,School of Microelectronics,Shanghai,China,200433","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5061769699"],"corresponding_institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4210132426","https://openalex.org/I4391767673"],"apc_list":null,"apc_paid":null,"fwci":0.2664,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.56710041,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6566296815872192},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34129559993743896},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3327997922897339}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6566296815872192},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34129559993743896},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3327997922897339}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon58565.2023.10396414","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon58565.2023.10396414","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4699999988079071}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W2382290278","https://openalex.org/W2350741829","https://openalex.org/W2530322880","https://openalex.org/W1596801655","https://openalex.org/W2359140296"],"abstract_inverted_index":{"As":[0],"design":[1,15,28,73,96],"goes":[2],"into":[3],"multi-billion":[4],"transistors,":[5],"the":[6,23,43,65,116],"synthesis":[7,24,31,78,118],"runtime":[8],"becomes":[9],"an":[10],"important":[11],"issue,":[12],"particularly":[13],"for":[14,38,80],"verification":[16],"and":[17,86,112],"prototyping,":[18],"as":[19],"one":[20],"may":[21,54],"run":[22],"many":[25],"times":[26],"with":[27,32],"change.":[29],"Module-by-module":[30],"multi-threading":[33],"is":[34],"a":[35,72],"natural":[36],"solution":[37],"fast":[39],"synthesis,":[40],"however,":[41],"at":[42],"cost":[44],"of":[45,47,64],"quality":[46],"results":[48,100,107],"(QoR)":[49],"degradation.":[50],"Besides,":[51],"multi-thread":[52,77],"speedup":[53,114],"not":[55],"be":[56],"so":[57],"good":[58],"due":[59],"to":[60,92],"very":[61],"uneven":[62],"sizes":[63],"modules.":[66,97],"In":[67],"this":[68],"paper,":[69],"we":[70],"propose":[71],"hierarchy":[74],"restructuring":[75],"based":[76],"algorithm":[79,104],"large-scale":[81],"designs.":[82],"Small":[83],"module":[84,88],"flattening":[85],"large":[87],"partitioning":[89],"are":[90],"used":[91],"create":[93],"moderate":[94],"size":[95],"Our":[98],"experimental":[99],"show":[101],"that":[102],"our":[103],"can":[105],"produce":[106],"within":[108],"3%":[109],"area":[110],"increase":[111],"21.3x":[113],"over":[115],"flat":[117],"flow.":[119]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1}],"updated_date":"2026-03-09T08:58:05.943551","created_date":"2025-10-10T00:00:00"}
