{"id":"https://openalex.org/W4391183635","doi":"https://doi.org/10.1109/asicon58565.2023.10396051","title":"A General-Purpose Compiler Design for Instruction-Based AI Accelerator Implementation","display_name":"A General-Purpose Compiler Design for Instruction-Based AI Accelerator Implementation","publication_year":2023,"publication_date":"2023-10-24","ids":{"openalex":"https://openalex.org/W4391183635","doi":"https://doi.org/10.1109/asicon58565.2023.10396051"},"language":"en","primary_location":{"id":"doi:10.1109/asicon58565.2023.10396051","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon58565.2023.10396051","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054738293","display_name":"Mengxuan Wang","orcid":"https://orcid.org/0009-0008-1392-2836"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Mengxuan Wang","raw_affiliation_strings":["Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5093780630","display_name":"Yuan Linghu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuan Linghu","raw_affiliation_strings":["Shanghai Fudan Microelectronics Group Co., Ltd.,Shanghai,China","Shanghai Fudan Microelectronics Group Co., Ltd., Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Shanghai Fudan Microelectronics Group Co., Ltd.,Shanghai,China","institution_ids":["https://openalex.org/I4210132426"]},{"raw_affiliation_string":"Shanghai Fudan Microelectronics Group Co., Ltd., Shanghai, China","institution_ids":["https://openalex.org/I4210132426"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101530541","display_name":"Chang Wu","orcid":"https://orcid.org/0000-0003-2590-6338"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chang Wu","raw_affiliation_strings":["Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5054738293"],"corresponding_institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"],"apc_list":null,"apc_paid":null,"fwci":0.123,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.46014872,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8760488033294678},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.8568440079689026},{"id":"https://openalex.org/keywords/compiler-correctness","display_name":"Compiler correctness","score":0.661664605140686},{"id":"https://openalex.org/keywords/optimizing-compiler","display_name":"Optimizing compiler","score":0.6116311550140381},{"id":"https://openalex.org/keywords/compiler-construction","display_name":"Compiler construction","score":0.5468546748161316},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.49518218636512756},{"id":"https://openalex.org/keywords/loop-unrolling","display_name":"Loop unrolling","score":0.48809874057769775},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4751793444156647},{"id":"https://openalex.org/keywords/interprocedural-optimization","display_name":"Interprocedural optimization","score":0.4442817270755768},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3169609308242798},{"id":"https://openalex.org/keywords/loop-optimization","display_name":"Loop optimization","score":0.24134215712547302}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8760488033294678},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.8568440079689026},{"id":"https://openalex.org/C68366613","wikidata":"https://www.wikidata.org/wiki/Q5156378","display_name":"Compiler correctness","level":3,"score":0.661664605140686},{"id":"https://openalex.org/C190902152","wikidata":"https://www.wikidata.org/wiki/Q1325106","display_name":"Optimizing compiler","level":3,"score":0.6116311550140381},{"id":"https://openalex.org/C9957790","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler construction","level":3,"score":0.5468546748161316},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.49518218636512756},{"id":"https://openalex.org/C76970557","wikidata":"https://www.wikidata.org/wiki/Q1869750","display_name":"Loop unrolling","level":3,"score":0.48809874057769775},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4751793444156647},{"id":"https://openalex.org/C111564260","wikidata":"https://www.wikidata.org/wiki/Q4288856","display_name":"Interprocedural optimization","level":5,"score":0.4442817270755768},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3169609308242798},{"id":"https://openalex.org/C29331672","wikidata":"https://www.wikidata.org/wiki/Q3354468","display_name":"Loop optimization","level":4,"score":0.24134215712547302}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon58565.2023.10396051","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon58565.2023.10396051","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W2119144962","https://openalex.org/W2155893237","https://openalex.org/W2276486856","https://openalex.org/W2787884921","https://openalex.org/W2793950911","https://openalex.org/W2809624076","https://openalex.org/W2810861508","https://openalex.org/W2962735857","https://openalex.org/W2963674932","https://openalex.org/W3011573341","https://openalex.org/W3117963962","https://openalex.org/W4214498565","https://openalex.org/W4281720481","https://openalex.org/W6638632666","https://openalex.org/W6677580257","https://openalex.org/W6753069482"],"related_works":["https://openalex.org/W2094199724","https://openalex.org/W4246454774","https://openalex.org/W2169584677","https://openalex.org/W4232954277","https://openalex.org/W4240253816","https://openalex.org/W2121223013","https://openalex.org/W2749133591","https://openalex.org/W2374859588","https://openalex.org/W2078984893","https://openalex.org/W2083681681"],"abstract_inverted_index":{"With":[0],"the":[1,8,20,83],"rapid":[2],"advancement":[3],"of":[4,11,22,67],"deep":[5],"neural":[6],"networks,":[7],"automatic":[9],"generation":[10],"accelerator":[12,42,95],"design":[13,38],"is":[14,79],"a":[15,34],"very":[16],"important":[17],"problem":[18],"for":[19,26,39,52,62],"deployment":[21],"AI":[23],"applications,":[24],"especially":[25],"edge":[27],"computation.":[28],"In":[29],"this":[30],"paper,":[31],"we":[32],"propose":[33],"general":[35],"purpose":[36],"compiler":[37,45,92,101],"instruction-based":[40],"CNN":[41],"design.":[43],"Our":[44],"incorporates":[46],"network":[47],"pruning":[48],"and":[49,58,70,74,86,105,109],"quantization":[50],"capabilities":[51],"better":[53,111],"performance.":[54],"CDFG-based":[55],"layer":[56],"fusion":[57],"scheduling":[59],"are":[60],"used":[61,80,99],"heterogeneous":[63],"computing":[64],"with":[65],"consideration":[66],"data":[68,87],"transformation":[69],"synchronization":[71],"between":[72],"CPU":[73],"accelerator.":[75],"A":[76],"device":[77],"file":[78],"to":[81,102],"define":[82],"instruction":[84],"set":[85],"space":[88],"so":[89],"that":[90],"our":[91,100],"supports":[93],"various":[94],"designs":[96],"uniformly.":[97],"We":[98],"implement":[103],"VGG16":[104],"yolo2":[106],"in":[107],"FPGAs":[108],"achieved":[110],"performance":[112],"than":[113],"existing":[114],"designs.":[115]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}