{"id":"https://openalex.org/W4391183751","doi":"https://doi.org/10.1109/asicon58565.2023.10395964","title":"Efficient FPGA Routing Architecture Exploration Based on Two-Stage MUXes","display_name":"Efficient FPGA Routing Architecture Exploration Based on Two-Stage MUXes","publication_year":2023,"publication_date":"2023-10-24","ids":{"openalex":"https://openalex.org/W4391183751","doi":"https://doi.org/10.1109/asicon58565.2023.10395964"},"language":"en","primary_location":{"id":"doi:10.1109/asicon58565.2023.10395964","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/asicon58565.2023.10395964","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076716353","display_name":"Jide Zhang","orcid":"https://orcid.org/0009-0005-5195-8176"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jide Zhang","raw_affiliation_strings":["Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059055868","display_name":"Kaixiang Zhu","orcid":"https://orcid.org/0000-0001-9361-4797"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kaixiang Zhu","raw_affiliation_strings":["Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075312901","display_name":"Kaichuang Shi","orcid":"https://orcid.org/0000-0002-6343-2930"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kaichuang Shi","raw_affiliation_strings":["Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002732486","display_name":"Lingli Wang","orcid":"https://orcid.org/0000-0002-0579-3527"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lingli Wang","raw_affiliation_strings":["Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100396802","display_name":"Hao Zhou","orcid":"https://orcid.org/0000-0001-7339-9006"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hao Zhou","raw_affiliation_strings":["Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Laboratory of ASIC and System,Shanghai,China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5076716353"],"corresponding_institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18378405,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7229308485984802},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7001298666000366},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6565731167793274},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6436042785644531},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6005455255508423},{"id":"https://openalex.org/keywords/stage","display_name":"Stage (stratigraphy)","score":0.45460906624794006},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4499666094779968},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33142441511154175},{"id":"https://openalex.org/keywords/geology","display_name":"Geology","score":0.11422455310821533},{"id":"https://openalex.org/keywords/geography","display_name":"Geography","score":0.06714421510696411}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7229308485984802},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7001298666000366},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6565731167793274},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6436042785644531},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6005455255508423},{"id":"https://openalex.org/C146357865","wikidata":"https://www.wikidata.org/wiki/Q1123245","display_name":"Stage (stratigraphy)","level":2,"score":0.45460906624794006},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4499666094779968},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33142441511154175},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.11422455310821533},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.06714421510696411},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon58565.2023.10395964","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/asicon58565.2023.10395964","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 15th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4200391368","https://openalex.org/W2110265185","https://openalex.org/W3146360095","https://openalex.org/W2184011203","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2160474882","https://openalex.org/W2154356865"],"abstract_inverted_index":{"Employing":[0],"large":[1,177],"routing":[2,56,179],"multiplexers":[3],"(MUXes)":[4],"in":[5,8,68,110],"FPGA":[6],"results":[7],"significant":[9],"area":[10,25,171],"and":[11,26,72,147],"delay":[12,27,167],"overheads.":[13],"Hence,":[14],"the":[15,24,30,81,90,96,111,149,157,175],"two-stage":[16,35,66,135],"cascaded":[17],"structure":[18],"with":[19,168],"small":[20],"MUXes":[21,67],"can":[22,79,141],"reduce":[23],"effectively.":[28],"However,":[29],"manual":[31,126],"design":[32],"of":[33,65,92,98,106,156],"a":[34,54,103,121,143,169],"MUX":[36,60,136,178],"topology":[37],"is":[38,50,117,131],"challenging":[39],"to":[40,83,102,124,174],"find":[41],"optimal":[42],"architecture.":[43,112,180],"An":[44],"automatic":[45],"switch":[46,69,93,107,115,145,158],"pattern":[47,116,129,146,150],"exploration":[48,139],"framework":[49,78,140],"proposed":[51],"based":[52,88],"on":[53,89],"novel":[55],"architecture,":[57],"TSRB":[58,114,144],"(Two-Stage":[59],"Routing":[61],"Block),":[62],"which":[63],"consists":[64],"box":[70],"(SB)":[71],"local":[73],"interconnection":[74],"block":[75],"(LIB).":[76],"The":[77,113,128],"enable":[80],"router":[82],"select":[84],"commonly":[85],"used":[86,109],"switches":[87],"usage":[91],"connections":[94],"under":[95],"premise":[97],"solving":[99],"congestion,":[100],"leading":[101],"minimal":[104],"set":[105],"types":[108],"generated":[118],"aided":[119],"by":[120,134,151],"pre-exploration":[122],"method":[123],"avoid":[125],"design.":[127],"optimization":[130],"then":[132],"followed":[133],"exploration.":[137],"Our":[138],"generate":[142],"optimize":[148],"pruning":[152],"more":[153],"than":[154],"half":[155],"connections,":[159],"achieving":[160],"an":[161],"average":[162],"7%":[163],"shorter":[164],"critical":[165],"path":[166],"5%":[170],"reduction":[172],"compared":[173],"one-stage":[176]},"counts_by_year":[],"updated_date":"2025-12-21T01:58:51.020947","created_date":"2025-10-10T00:00:00"}
