{"id":"https://openalex.org/W4200380016","doi":"https://doi.org/10.1109/asicon52560.2021.9620479","title":"New Linearization Implementations Improving IIP3 of Wideband LNTA by More than 14dB","display_name":"New Linearization Implementations Improving IIP3 of Wideband LNTA by More than 14dB","publication_year":2021,"publication_date":"2021-10-26","ids":{"openalex":"https://openalex.org/W4200380016","doi":"https://doi.org/10.1109/asicon52560.2021.9620479"},"language":"en","primary_location":{"id":"doi:10.1109/asicon52560.2021.9620479","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon52560.2021.9620479","pdf_url":null,"source":{"id":"https://openalex.org/S4363607945","display_name":"2021 IEEE 14th International Conference on ASIC (ASICON)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE 14th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051368557","display_name":"Cong Tao","orcid":"https://orcid.org/0000-0001-7402-1427"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Cong Tao","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023180065","display_name":"Liangbo Lei","orcid":"https://orcid.org/0009-0002-0675-4711"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liangbo Lei","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082912188","display_name":"Jiangli Huang","orcid":"https://orcid.org/0000-0001-9111-8474"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jiangli Huang","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100325084","display_name":"Zhipeng Chen","orcid":"https://orcid.org/0000-0002-8330-0070"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhipeng Chen","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101872560","display_name":"Yumei Huang","orcid":"https://orcid.org/0009-0009-6376-5362"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yumei Huang","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082092557","display_name":"Zhiliang Hong","orcid":"https://orcid.org/0000-0002-9968-5964"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhiliang Hong","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5051368557"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":1.731,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.83717964,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11160","display_name":"Acoustic Wave Resonator Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.71770179271698},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6701282262802124},{"id":"https://openalex.org/keywords/linearization","display_name":"Linearization","score":0.6475427150726318},{"id":"https://openalex.org/keywords/wideband","display_name":"Wideband","score":0.6394631862640381},{"id":"https://openalex.org/keywords/transconductance","display_name":"Transconductance","score":0.5919001698493958},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5059460997581482},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.468919575214386},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.4632718563079834},{"id":"https://openalex.org/keywords/resistor","display_name":"Resistor","score":0.44466203451156616},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.367587685585022},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.28893691301345825},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.27707087993621826},{"id":"https://openalex.org/keywords/nonlinear-system","display_name":"Nonlinear system","score":0.1606403887271881},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1499028503894806},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.10953432321548462}],"concepts":[{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.71770179271698},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6701282262802124},{"id":"https://openalex.org/C11210021","wikidata":"https://www.wikidata.org/wiki/Q1520713","display_name":"Linearization","level":3,"score":0.6475427150726318},{"id":"https://openalex.org/C2780202535","wikidata":"https://www.wikidata.org/wiki/Q4524457","display_name":"Wideband","level":2,"score":0.6394631862640381},{"id":"https://openalex.org/C2779283907","wikidata":"https://www.wikidata.org/wiki/Q1632964","display_name":"Transconductance","level":4,"score":0.5919001698493958},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5059460997581482},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.468919575214386},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.4632718563079834},{"id":"https://openalex.org/C137488568","wikidata":"https://www.wikidata.org/wiki/Q5321","display_name":"Resistor","level":3,"score":0.44466203451156616},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.367587685585022},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.28893691301345825},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.27707087993621826},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.1606403887271881},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1499028503894806},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.10953432321548462},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon52560.2021.9620479","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon52560.2021.9620479","pdf_url":null,"source":{"id":"https://openalex.org/S4363607945","display_name":"2021 IEEE 14th International Conference on ASIC (ASICON)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE 14th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1991722653","https://openalex.org/W2123563838","https://openalex.org/W2148789056","https://openalex.org/W2292570254","https://openalex.org/W2588662529","https://openalex.org/W2897033281","https://openalex.org/W3163545370"],"related_works":["https://openalex.org/W2548900738","https://openalex.org/W4388638935","https://openalex.org/W1995167383","https://openalex.org/W2015135688","https://openalex.org/W4238016235","https://openalex.org/W4367147734","https://openalex.org/W3094419935","https://openalex.org/W4399327775","https://openalex.org/W2126749882","https://openalex.org/W4253758303"],"abstract_inverted_index":{"High":[0],"linearity":[1,16,91],"low":[2],"noise":[3],"transconductance":[4],"amplifier":[5],"(LNTA)":[6],"is":[7,23,44],"very":[8,25],"important":[9],"for":[10],"wideband":[11],"SAW-less":[12],"receivers(RX),":[13],"but":[14],"the":[15,40,64,79,82,96,102,107,110],"of":[17,39,66,81,109],"LNTA":[18,111],"realized":[19],"by":[20,115,119],"CMOS":[21],"process":[22],"generally":[24],"poor.":[26],"In":[27],"order":[28],"to":[29,62],"meet":[30],"specific":[31],"requirements,":[32],"linearization":[33],"techniques":[34],"are":[35],"usually":[36],"necessary.":[37],"One":[38],"most":[41],"commonly-used":[42],"methods":[43],"derivative":[45],"superposition(DS),":[46],"which":[47,94],"can":[48,112],"effectively":[49],"improve":[50],"IIP3.":[51],"The":[52],"traditional":[53,83],"DS":[54,84],"method":[55],"uses":[56],"a":[57],"resistor":[58],"and":[59,72],"capacitor":[60],"network":[61],"bias":[63,74],"gate":[65],"MOSFET,":[67],"occupying":[68],"additional":[69],"chip":[70],"area":[71],"complicating":[73],"circuit":[75,97],"design.":[76,98],"Based":[77],"on":[78],"principle":[80],"method,":[85],"this":[86],"paper":[87],"proposes":[88],"three":[89],"new":[90],"compensation":[92],"implementations,":[93],"simplify":[95],"Under":[99],"TSMC40nmLP":[100],"process,":[101],"simulation":[103],"results":[104],"show":[105],"that":[106],"IIP3":[108],"be":[113],"increased":[114],"more":[116],"than":[117],"14dB":[118],"using":[120],"these":[121],"implementations.":[122]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
