{"id":"https://openalex.org/W4200371803","doi":"https://doi.org/10.1109/asicon52560.2021.9620445","title":"Pitch Device Design in 10nm-Class DRAM Process through DTCO","display_name":"Pitch Device Design in 10nm-Class DRAM Process through DTCO","publication_year":2021,"publication_date":"2021-10-26","ids":{"openalex":"https://openalex.org/W4200371803","doi":"https://doi.org/10.1109/asicon52560.2021.9620445"},"language":"en","primary_location":{"id":"doi:10.1109/asicon52560.2021.9620445","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon52560.2021.9620445","pdf_url":null,"source":{"id":"https://openalex.org/S4363607945","display_name":"2021 IEEE 14th International Conference on ASIC (ASICON)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE 14th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109862350","display_name":"Yanzhe Tang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yanzhe Tang","raw_affiliation_strings":["Product Research and Development, Changxin Memory Technologies, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Product Research and Development, Changxin Memory Technologies, Shanghai, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100728381","display_name":"Zhongming Liu","orcid":"https://orcid.org/0000-0002-0146-8188"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zhongming Liu","raw_affiliation_strings":["Unit Process Development, Changxin Memory Technologies, Hefei, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Unit Process Development, Changxin Memory Technologies, Hefei, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077741864","display_name":"Weibing Shang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Weibing Shang","raw_affiliation_strings":["Product Research and Development, Changxin Memory Technologies, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Product Research and Development, Changxin Memory Technologies, Shanghai, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103051745","display_name":"Fengqin Zhang","orcid":"https://orcid.org/0000-0002-8969-0807"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Fengqin Zhang","raw_affiliation_strings":["Product Research and Development, Changxin Memory Technologies, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Product Research and Development, Changxin Memory Technologies, Shanghai, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103528923","display_name":"Bernard Wu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Bernard Wu","raw_affiliation_strings":["Product Research and Development, Changxin Memory Technologies, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Product Research and Development, Changxin Memory Technologies, Shanghai, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003969809","display_name":"Zhong Hua Kong","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zhong Kong","raw_affiliation_strings":["Unit Process Development, Changxin Memory Technologies, Hefei, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Unit Process Development, Changxin Memory Technologies, Hefei, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101702714","display_name":"Hongwen Li","orcid":"https://orcid.org/0000-0001-6698-2797"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hongwen Li","raw_affiliation_strings":["Product Research and Development, Changxin Memory Technologies, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Product Research and Development, Changxin Memory Technologies, Shanghai, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058808832","display_name":"Hong Ma","orcid":"https://orcid.org/0000-0001-6414-8870"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hong Ma","raw_affiliation_strings":["Unit Process Development, Changxin Memory Technologies, Hefei, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Unit Process Development, Changxin Memory Technologies, Hefei, China","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053073618","display_name":"Kanyu Cao","orcid":"https://orcid.org/0000-0002-1931-6836"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kanyu Cao","raw_affiliation_strings":["Product Research and Development, Changxin Memory Technologies, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Product Research and Development, Changxin Memory Technologies, Shanghai, China","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.407,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.54819172,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.9071944952011108},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6670769453048706},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.6657631397247314},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.6446689367294312},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.6097726821899414},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5645535588264465},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5360022187232971},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4930107295513153},{"id":"https://openalex.org/keywords/data-retention","display_name":"Data retention","score":0.46689924597740173},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44346413016319275},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4272928833961487},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4245384931564331},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.408674031496048},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3299613893032074},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2851998805999756},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21432775259017944},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12229800224304199},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07691004872322083}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.9071944952011108},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6670769453048706},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.6657631397247314},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.6446689367294312},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.6097726821899414},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5645535588264465},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5360022187232971},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4930107295513153},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.46689924597740173},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44346413016319275},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4272928833961487},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4245384931564331},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.408674031496048},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3299613893032074},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2851998805999756},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21432775259017944},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12229800224304199},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07691004872322083},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon52560.2021.9620445","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon52560.2021.9620445","pdf_url":null,"source":{"id":"https://openalex.org/S4363607945","display_name":"2021 IEEE 14th International Conference on ASIC (ASICON)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE 14th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.49000000953674316,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W3130092517"],"related_works":["https://openalex.org/W2074922484","https://openalex.org/W2063061014","https://openalex.org/W2130607063","https://openalex.org/W2149227206","https://openalex.org/W2473808647","https://openalex.org/W2001316072","https://openalex.org/W3004383742","https://openalex.org/W2105633922","https://openalex.org/W2540867894","https://openalex.org/W2067914900"],"abstract_inverted_index":{"The":[0],"challenge":[1],"for":[2,31],"the":[3,15,39,47,59,71,88,98,102],"pitch":[4,33,45],"device":[5,89],"design":[6,70],"in":[7,75],"Dynamic-":[8],"Random-Access-Memory":[9],"(DRAM)":[10],"chip":[11],"is":[12,28],"increasing":[13],"with":[14,50,114],"technology":[16],"node":[17],"continuing":[18],"scaling":[19],"down":[20],"to":[21,100],"15nm":[22],"and":[23,42,53,85,93,96],"below.":[24],"DTCO":[25],"(Design-Technology-Co-":[26],"Optimization":[27],"a":[29,76],"must":[30],"designing":[32],"devices,":[34],"which":[35,111],"can":[36],"fit":[37],"into":[38,80],"word-line":[40],"(WL)":[41],"bit-line":[43],"(BL)":[44],"of":[46,82],"memory":[48],"array,":[49],"satisfactory":[51],"electrical":[52],"sufficient":[54],"reliability":[55,94],"performance,":[56],"while":[57],"occupies":[58],"smallest":[60],"area.":[61],"In":[62],"this":[63],"paper,":[64],"we":[65,69],"will":[66],"show":[67],"how":[68],"sub-wordline-driver":[72],"(SWD)":[73],"devices":[74],"DRAM":[77],"chip,":[78],"taking":[79],"account":[81],"process":[83,115],"limitations":[84],"variations,":[86],"balancing":[87],"between":[90],"on/off":[91],"performance":[92],"requirements,":[95],"optimizing":[97],"circuits":[99],"reduce":[101],"hot-carrier-injection":[103],"(HCI)":[104],"stress,":[105],"by":[106],"utilizing":[107],"different":[108],"simulation":[109],"tools":[110],"are":[112],"calibrated":[113],"data.":[116]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}