{"id":"https://openalex.org/W3005031353","doi":"https://doi.org/10.1109/asicon47005.2019.8983675","title":"A 16/32Gb/s NRZ/PAM4 Receiver with Dual-Loop CDR and Threshold Voltage Calibration","display_name":"A 16/32Gb/s NRZ/PAM4 Receiver with Dual-Loop CDR and Threshold Voltage Calibration","publication_year":2019,"publication_date":"2019-10-01","ids":{"openalex":"https://openalex.org/W3005031353","doi":"https://doi.org/10.1109/asicon47005.2019.8983675","mag":"3005031353"},"language":"en","primary_location":{"id":"doi:10.1109/asicon47005.2019.8983675","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon47005.2019.8983675","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 13th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057833298","display_name":"Songhao Guo","orcid":"https://orcid.org/0000-0003-0570-0164"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Songhao Guo","raw_affiliation_strings":["Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics Shanghai Jiaotong University,Shanghai,China,200240","Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics Shanghai Jiaotong University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics Shanghai Jiaotong University,Shanghai,China,200240","institution_ids":["https://openalex.org/I183067930"]},{"raw_affiliation_string":"Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics Shanghai Jiaotong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101945600","display_name":"Li Ding","orcid":"https://orcid.org/0000-0001-6367-0333"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Li Ding","raw_affiliation_strings":["Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics Shanghai Jiaotong University,Shanghai,China,200240","Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics Shanghai Jiaotong University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics Shanghai Jiaotong University,Shanghai,China,200240","institution_ids":["https://openalex.org/I183067930"]},{"raw_affiliation_string":"Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics Shanghai Jiaotong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052970732","display_name":"Jing Jin","orcid":"https://orcid.org/0000-0003-3584-5559"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jing Jin","raw_affiliation_strings":["Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics Shanghai Jiaotong University,Shanghai,China,200240","Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics Shanghai Jiaotong University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics Shanghai Jiaotong University,Shanghai,China,200240","institution_ids":["https://openalex.org/I183067930"]},{"raw_affiliation_string":"Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics Shanghai Jiaotong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I183067930"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9944000244140625,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7624663710594177},{"id":"https://openalex.org/keywords/serdes","display_name":"SerDes","score":0.6561054587364197},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6275386810302734},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5842118859291077},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.551404595375061},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.4789448380470276},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.473509818315506},{"id":"https://openalex.org/keywords/intersymbol-interference","display_name":"Intersymbol interference","score":0.45713838934898376},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.3502455949783325},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25268757343292236},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12419813871383667}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7624663710594177},{"id":"https://openalex.org/C19707634","wikidata":"https://www.wikidata.org/wiki/Q6510662","display_name":"SerDes","level":2,"score":0.6561054587364197},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6275386810302734},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5842118859291077},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.551404595375061},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.4789448380470276},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.473509818315506},{"id":"https://openalex.org/C97812054","wikidata":"https://www.wikidata.org/wiki/Q2166055","display_name":"Intersymbol interference","level":3,"score":0.45713838934898376},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.3502455949783325},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25268757343292236},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12419813871383667}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon47005.2019.8983675","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon47005.2019.8983675","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 13th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1592084739","https://openalex.org/W4229627422","https://openalex.org/W4408183178"],"related_works":["https://openalex.org/W1933111953","https://openalex.org/W2003312501","https://openalex.org/W2091946342","https://openalex.org/W1520599922","https://openalex.org/W2510718891","https://openalex.org/W2118455460","https://openalex.org/W2126574816","https://openalex.org/W1994021281","https://openalex.org/W2624154251","https://openalex.org/W2102417914"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,12],"reconfigurable":[4],"dual-mode":[5],"NRZ/PAM4":[6],"wireline":[7],"receiver.":[8],"The":[9,70,114],"receiver":[10,71,93],"implements":[11],"two-stage":[13],"continuous":[14],"time":[15],"linear":[16],"equalizer":[17,23],"(CTLE)":[18],"and":[19,28,38,42,52,61,67,82,104],"half-rate":[20],"decision":[21],"feedback":[22],"(DFE)":[24],"to":[25,48],"extend":[26],"bandwidth":[27],"achieve":[29],"inter-symbol":[30],"interference":[31],"(ISI)":[32],"cancellation,":[33],"respectively.":[34],"Compatible":[35],"dual-loop":[36],"clock":[37,51,119],"data":[39],"recovery":[40],"(CDR)":[41],"Gray":[43],"code-based":[44],"decoder":[45],"are":[46],"used":[47],"generate":[49],"multi-phase":[50],"calibrate":[53],"DFE":[54],"threshold":[55],"voltages.":[56],"Its":[57],"high":[58],"hardware":[59],"reusability":[60],"flexibility":[62],"greatly":[63],"reduce":[64],"power":[65],"consumption":[66],"chip":[68],"area.":[69],"is":[72,99,123],"verified":[73],"in":[74,101,108],"22nm":[75],"CMOS":[76],"FDSOI":[77],"technology":[78],"with":[79],"0.8V":[80],"supply,":[81],"the":[83,92],"simulation":[84],"results":[85],"through":[86],"moderate":[87],"lossy":[88],"channel":[89],"indicate":[90],"that":[91],"achieves":[94],"reasonable":[95],"eye":[96],"opening,":[97],"which":[98],"300mVpp":[100],"NRZ":[102],"mode":[103,110],"80":[105],"mVpp(per":[106],"eye)":[107],"PAM4":[109],"after":[111,120],"proper":[112],"equalization.":[113],"jitter":[115],"performance":[116],"of":[117],"8GHz":[118],"CDR":[121],"locked":[122],"1.95ps.":[124]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
