{"id":"https://openalex.org/W3004947623","doi":"https://doi.org/10.1109/asicon47005.2019.8983573","title":"UVM-based Functional Coverage Driven AXI4-Stream Verification","display_name":"UVM-based Functional Coverage Driven AXI4-Stream Verification","publication_year":2019,"publication_date":"2019-10-01","ids":{"openalex":"https://openalex.org/W3004947623","doi":"https://doi.org/10.1109/asicon47005.2019.8983573","mag":"3004947623"},"language":"en","primary_location":{"id":"doi:10.1109/asicon47005.2019.8983573","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon47005.2019.8983573","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 13th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101198972","display_name":"Chunlin Xu","orcid":null},"institutions":[{"id":"https://openalex.org/I16365422","display_name":"Hefei University of Technology","ror":"https://ror.org/02czkny70","country_code":"CN","type":"education","lineage":["https://openalex.org/I16365422"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Chunlin Xu","raw_affiliation_strings":["Institute of VLSI Design, Hefei University of Technology,Hefei,China,230601","Institute of VLSI Design, Hefei University of Technology, Hefei, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Hefei University of Technology,Hefei,China,230601","institution_ids":["https://openalex.org/I16365422"]},{"raw_affiliation_string":"Institute of VLSI Design, Hefei University of Technology, Hefei, China","institution_ids":["https://openalex.org/I16365422"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067935874","display_name":"Wei Ni","orcid":"https://orcid.org/0000-0002-1410-8317"},"institutions":[{"id":"https://openalex.org/I16365422","display_name":"Hefei University of Technology","ror":"https://ror.org/02czkny70","country_code":"CN","type":"education","lineage":["https://openalex.org/I16365422"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wei Ni","raw_affiliation_strings":["Institute of VLSI Design, Hefei University of Technology,Hefei,China,230601","Institute of VLSI Design, Hefei University of Technology, Hefei, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Hefei University of Technology,Hefei,China,230601","institution_ids":["https://openalex.org/I16365422"]},{"raw_affiliation_string":"Institute of VLSI Design, Hefei University of Technology, Hefei, China","institution_ids":["https://openalex.org/I16365422"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5114973839","display_name":"Yukun Song","orcid":"https://orcid.org/0009-0004-9843-3505"},"institutions":[{"id":"https://openalex.org/I16365422","display_name":"Hefei University of Technology","ror":"https://ror.org/02czkny70","country_code":"CN","type":"education","lineage":["https://openalex.org/I16365422"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yukun Song","raw_affiliation_strings":["Institute of VLSI Design, Hefei University of Technology,Hefei,China,230601","Institute of VLSI Design, Hefei University of Technology, Hefei, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Hefei University of Technology,Hefei,China,230601","institution_ids":["https://openalex.org/I16365422"]},{"raw_affiliation_string":"Institute of VLSI Design, Hefei University of Technology, Hefei, China","institution_ids":["https://openalex.org/I16365422"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101198972"],"corresponding_institution_ids":["https://openalex.org/I16365422"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.20375685,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12495","display_name":"Electrostatic Discharge in Electronics","score":0.9934999942779541,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9921000003814697,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.8794002532958984},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8086014986038208},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.7778081893920898},{"id":"https://openalex.org/keywords/high-level-verification","display_name":"High-level verification","score":0.5847089290618896},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.5774176120758057},{"id":"https://openalex.org/keywords/verification","display_name":"Verification","score":0.5676642060279846},{"id":"https://openalex.org/keywords/runtime-verification","display_name":"Runtime verification","score":0.5612495541572571},{"id":"https://openalex.org/keywords/software-verification","display_name":"Software verification","score":0.5271201729774475},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.511466383934021},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4334743618965149},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.41036808490753174},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.19988083839416504},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.19463911652565002},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.1882624626159668}],"concepts":[{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.8794002532958984},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8086014986038208},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.7778081893920898},{"id":"https://openalex.org/C187250869","wikidata":"https://www.wikidata.org/wiki/Q5754573","display_name":"High-level verification","level":5,"score":0.5847089290618896},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.5774176120758057},{"id":"https://openalex.org/C142284323","wikidata":"https://www.wikidata.org/wiki/Q7921323","display_name":"Verification","level":5,"score":0.5676642060279846},{"id":"https://openalex.org/C202973057","wikidata":"https://www.wikidata.org/wiki/Q7380130","display_name":"Runtime verification","level":3,"score":0.5612495541572571},{"id":"https://openalex.org/C33054407","wikidata":"https://www.wikidata.org/wiki/Q6504747","display_name":"Software verification","level":5,"score":0.5271201729774475},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.511466383934021},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4334743618965149},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.41036808490753174},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.19988083839416504},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.19463911652565002},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.1882624626159668},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon47005.2019.8983573","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon47005.2019.8983573","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 13th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.46000000834465027,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2535974818","https://openalex.org/W2899682454","https://openalex.org/W2921894752","https://openalex.org/W2945879635","https://openalex.org/W6728722040"],"related_works":["https://openalex.org/W2361881307","https://openalex.org/W2392047570","https://openalex.org/W4205300843","https://openalex.org/W2035244079","https://openalex.org/W3036403349","https://openalex.org/W2355428260","https://openalex.org/W4301348901","https://openalex.org/W2350806125","https://openalex.org/W3120172095","https://openalex.org/W4214538333"],"abstract_inverted_index":{"With":[0,53],"the":[1,22,66],"increasing":[2],"complexity":[3],"of":[4,32,39,68],"modern":[5],"silicon":[6],"chips,":[7],"verification":[8,17,34,42,70,90],"for":[9],"SoCs":[10,84],"is":[11,25,48,72],"also":[12],"facing":[13],"huge":[14],"challenges.":[15],"Traditional":[16],"methodologies":[18],"which":[19],"cannot":[20],"meet":[21],"time-to-market":[23],"requirement":[24],"being":[26],"replaced":[27],"by":[28],"UVM,":[29],"a":[30],"state":[31],"art":[33],"methodology.":[35],"An":[36],"UVM-based":[37],"out":[38],"box":[40],"AX14-Stream":[41,86],"IP":[43,71,81],"featuring":[44,85],"functional":[45],"coverage":[46],"model":[47],"designed":[49],"in":[50],"this":[51,69],"paper.":[52],"constrained":[54],"random":[55],"test,":[56,61],"base":[57],"test":[58],"and":[59,74,83],"direct":[60],"simulation":[62],"results":[63],"show":[64],"that":[65],"function":[67],"correct":[73],"can":[75],"be":[76],"used":[77],"to":[78],"verify":[79],"any":[80],"cores":[82],"interface":[87],"with":[88],"improved":[89],"efficiency.":[91]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}