{"id":"https://openalex.org/W3005179204","doi":"https://doi.org/10.1109/asicon47005.2019.8983556","title":"A High-Linear Digital-to-Phase Converter in 40nm CMOS","display_name":"A High-Linear Digital-to-Phase Converter in 40nm CMOS","publication_year":2019,"publication_date":"2019-10-01","ids":{"openalex":"https://openalex.org/W3005179204","doi":"https://doi.org/10.1109/asicon47005.2019.8983556","mag":"3005179204"},"language":"en","primary_location":{"id":"doi:10.1109/asicon47005.2019.8983556","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon47005.2019.8983556","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 13th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048125506","display_name":"Ji Yu","orcid":"https://orcid.org/0000-0002-3500-8630"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yu Ji","raw_affiliation_strings":["School of Microelectronics, Shanghai Jiao Tong University,Shanghai,China,200240","School of Microelectronics, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Shanghai Jiao Tong University,Shanghai,China,200240","institution_ids":["https://openalex.org/I183067930"]},{"raw_affiliation_string":"School of Microelectronics, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101945600","display_name":"Li Ding","orcid":"https://orcid.org/0000-0001-6367-0333"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Li Ding","raw_affiliation_strings":["School of Microelectronics, Shanghai Jiao Tong University,Shanghai,China,200240","School of Microelectronics, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Shanghai Jiao Tong University,Shanghai,China,200240","institution_ids":["https://openalex.org/I183067930"]},{"raw_affiliation_string":"School of Microelectronics, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052970732","display_name":"Jing Jin","orcid":"https://orcid.org/0000-0003-3584-5559"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jing Jin","raw_affiliation_strings":["School of Microelectronics, Shanghai Jiao Tong University,Shanghai,China,200240","School of Microelectronics, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Shanghai Jiao Tong University,Shanghai,China,200240","institution_ids":["https://openalex.org/I183067930"]},{"raw_affiliation_string":"School of Microelectronics, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I183067930"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7508941292762756},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6144872903823853},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.6138803362846375},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.6115022897720337},{"id":"https://openalex.org/keywords/interpolation","display_name":"Interpolation (computer graphics)","score":0.5213443040847778},{"id":"https://openalex.org/keywords/phase","display_name":"Phase (matter)","score":0.5026826858520508},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.47032463550567627},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.45982077717781067},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.30512601137161255},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.27942681312561035},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24207088351249695},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.12767040729522705},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.11552128195762634},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11549597978591919},{"id":"https://openalex.org/keywords/frame","display_name":"Frame (networking)","score":0.09949469566345215}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7508941292762756},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6144872903823853},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.6138803362846375},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.6115022897720337},{"id":"https://openalex.org/C137800194","wikidata":"https://www.wikidata.org/wiki/Q11713455","display_name":"Interpolation (computer graphics)","level":3,"score":0.5213443040847778},{"id":"https://openalex.org/C44280652","wikidata":"https://www.wikidata.org/wiki/Q104837","display_name":"Phase (matter)","level":2,"score":0.5026826858520508},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.47032463550567627},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.45982077717781067},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.30512601137161255},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.27942681312561035},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24207088351249695},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.12767040729522705},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.11552128195762634},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11549597978591919},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.09949469566345215},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon47005.2019.8983556","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon47005.2019.8983556","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 13th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6499999761581421,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2072864093","https://openalex.org/W2166826967","https://openalex.org/W2516199239","https://openalex.org/W2788680135","https://openalex.org/W3159572620"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W2097523295","https://openalex.org/W4360861688","https://openalex.org/W3134930219","https://openalex.org/W984417604","https://openalex.org/W2967785526","https://openalex.org/W2908000842","https://openalex.org/W2065391525","https://openalex.org/W2113001378","https://openalex.org/W2113057816"],"abstract_inverted_index":{"A":[0],"high":[1],"linear":[2],"digital-to-phase":[3],"converter":[4],"(DPC)":[5],"with":[6,71],"7-bit":[7],"resolution":[8],"is":[9,31,47,57],"presented":[10],"in":[11,33,59,67],"this":[12],"paper.":[13],"The":[14,29,55],"DPC":[15,56],"consists":[16],"of":[17],"duty":[18],"cycle":[19],"corrector":[20],"(DCC),":[21],"delay-locked":[22],"loop":[23],"(DLL)":[24],"and":[25,64],"phase":[26,38,53],"interpolator":[27],"(PI).":[28],"interpolation":[30],"analyzed":[32],"detail,":[34],"describing":[35],"that":[36],"reducing":[37],"interval":[39],"can":[40],"improve":[41],"linearity.":[42],"Furthermore,":[43],"nonlinear":[44],"weighting":[45],"technology":[46,63],"employed":[48],"to":[49],"suppress":[50],"the":[51],"systematic":[52],"error.":[54],"implemented":[58],"standard":[60],"40nm":[61],"CMOS":[62],"consumes":[65],"7.5mA":[66],"a":[68,72],"1.1-V":[69],"supply":[70],"DNL":[73],"less":[74],"than":[75],"13.2%.":[76]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}