{"id":"https://openalex.org/W3004637870","doi":"https://doi.org/10.1109/asicon47005.2019.8983553","title":"A Low-delay Configurable Register for FPGA","display_name":"A Low-delay Configurable Register for FPGA","publication_year":2019,"publication_date":"2019-10-01","ids":{"openalex":"https://openalex.org/W3004637870","doi":"https://doi.org/10.1109/asicon47005.2019.8983553","mag":"3004637870"},"language":"en","primary_location":{"id":"doi:10.1109/asicon47005.2019.8983553","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon47005.2019.8983553","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 13th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068915961","display_name":"Zhiyin Lu","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhi-Yin Lu","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University,Shanghai,China,200433","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University,Shanghai,China,200433","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101726410","display_name":"Jiafeng Liu","orcid":"https://orcid.org/0009-0005-5530-8744"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jia-Feng Liu","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University,Shanghai,China,200433","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University,Shanghai,China,200433","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041398818","display_name":"Yunbing Pang","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yun-Bing Pang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University,Shanghai,China,200433","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University,Shanghai,China,200433","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085663994","display_name":"Zheug-Jie Li","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zheug-Jie Li","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University,Shanghai,China,200433","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University,Shanghai,China,200433","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110839622","display_name":"Yufan Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yu-Fan Zhang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University,Shanghai,China,200433","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University,Shanghai,China,200433","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081419061","display_name":"Jinmei Lai","orcid":"https://orcid.org/0009-0003-5238-4720"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jin-Mei Lai","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University,Shanghai,China,200433","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University,Shanghai,China,200433","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100758062","display_name":"Jian Wang","orcid":"https://orcid.org/0000-0003-3633-6799"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Wang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University,Shanghai,China,200433","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University,Shanghai,China,200433","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5068915961"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.2408,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.53626402,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9901999831199646,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.989300012588501,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7825747132301331},{"id":"https://openalex.org/keywords/register","display_name":"Register (sociolinguistics)","score":0.7118774652481079},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6934942007064819},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.6049615144729614},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3773185908794403},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3594557046890259},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34109342098236084},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11154589056968689}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7825747132301331},{"id":"https://openalex.org/C2779235478","wikidata":"https://www.wikidata.org/wiki/Q286576","display_name":"Register (sociolinguistics)","level":2,"score":0.7118774652481079},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6934942007064819},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.6049615144729614},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3773185908794403},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3594557046890259},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34109342098236084},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11154589056968689},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon47005.2019.8983553","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon47005.2019.8983553","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 13th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2065489212","https://openalex.org/W2120397377","https://openalex.org/W2126255765","https://openalex.org/W2148676074","https://openalex.org/W2392814083"],"related_works":["https://openalex.org/W4312941541","https://openalex.org/W2361019053","https://openalex.org/W2071125430","https://openalex.org/W624979004","https://openalex.org/W4238987864","https://openalex.org/W4232669059","https://openalex.org/W2064119831","https://openalex.org/W1606827233","https://openalex.org/W2224948060","https://openalex.org/W2027480766"],"abstract_inverted_index":{"A":[0,85],"low-delay":[1],"configurable":[2,100,132],"register":[3,30,34,133],"for":[4],"FPGA":[5],"is":[6,13,87],"designed":[7],"in":[8],"this":[9,130],"paper.":[10],"This":[11],"design":[12],"based":[14],"on":[15,24],"the":[16,29,51,69,81,91,95,99,112,120,126],"basic":[17],"master-slave":[18,114],"D":[19,70,115],"flip-flop,":[20],"uses":[21],"transmission":[22],"gates":[23],"key":[25],"nodes":[26],"to":[27,49,111,140],"control":[28,66,76,121],"into":[31],"four":[32],"modes:":[33],"mode,":[35,37,44],"latch":[36],"synchronous":[38,58],"overwrite":[39,43],"mode":[40],"and":[41,63,68,94,146],"asynchronous":[42,60],"then":[45],"inputs":[46],"desired":[47],"signals":[48,67],"complete":[50],"functions":[52,103],"of":[53,138],"registers,":[54],"latches,":[55],"global":[56],"initialization,":[57],"reset,":[59,61],"capture":[62],"write-back.":[64],"The":[65,106],"input":[71],"are":[72,104,109],"separated":[73],"so":[74],"that":[75,98,119],"circuit":[77,122],"will":[78],"not":[79,124],"affect":[80,125],"register's":[82,101],"timing":[83,107,127],"parameters.":[84,128],"pre-simulation":[86],"carried":[88],"out":[89],"under":[90],"28nm":[92],"process":[93],"results":[96],"show":[97],"various":[102],"correct.":[105],"parameters":[108],"equivalent":[110],"non-configurable":[113],"flip-flops,":[116],"which":[117],"proves":[118],"does":[123],"In":[129],"paper,":[131],"has":[134],"a":[135,142,147],"41-ps":[136],"delay":[137],"CK":[139],"Q,":[141],"7-ps":[143],"setup":[144],"time":[145],"0-ps":[148],"hold":[149],"time.":[150]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
