{"id":"https://openalex.org/W3005363250","doi":"https://doi.org/10.1109/asicon47005.2019.8983527","title":"Improve DRAM Leakage Issue During RAS Operational Phase Through TCAD Simulation","display_name":"Improve DRAM Leakage Issue During RAS Operational Phase Through TCAD Simulation","publication_year":2019,"publication_date":"2019-10-01","ids":{"openalex":"https://openalex.org/W3005363250","doi":"https://doi.org/10.1109/asicon47005.2019.8983527","mag":"3005363250"},"language":"en","primary_location":{"id":"doi:10.1109/asicon47005.2019.8983527","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon47005.2019.8983527","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 13th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100772272","display_name":"Ning Li","orcid":"https://orcid.org/0000-0001-9014-5913"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Ning Li","raw_affiliation_strings":["Product Research and Development, ChangXin Memory Technologies, Inc.,Hefei,China,230000","Product Research and Development, ChangXin Memory Technologies, Inc., Hefei, China"],"affiliations":[{"raw_affiliation_string":"Product Research and Development, ChangXin Memory Technologies, Inc.,Hefei,China,230000","institution_ids":[]},{"raw_affiliation_string":"Product Research and Development, ChangXin Memory Technologies, Inc., Hefei, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109513363","display_name":"Wen-Yang Jiang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wen-Yang Jiang","raw_affiliation_strings":["Product Research and Development, ChangXin Memory Technologies, Inc.,Hefei,China,230000","Product Research and Development, ChangXin Memory Technologies, Inc., Hefei, China"],"affiliations":[{"raw_affiliation_string":"Product Research and Development, ChangXin Memory Technologies, Inc.,Hefei,China,230000","institution_ids":[]},{"raw_affiliation_string":"Product Research and Development, ChangXin Memory Technologies, Inc., Hefei, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108449418","display_name":"Blacksmith Wu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Blacksmith Wu","raw_affiliation_strings":["Product Research and Development, ChangXin Memory Technologies, Inc.,Hefei,China,230000","Product Research and Development, ChangXin Memory Technologies, Inc., Hefei, China"],"affiliations":[{"raw_affiliation_string":"Product Research and Development, ChangXin Memory Technologies, Inc.,Hefei,China,230000","institution_ids":[]},{"raw_affiliation_string":"Product Research and Development, ChangXin Memory Technologies, Inc., Hefei, China","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053073618","display_name":"Kanyu Cao","orcid":"https://orcid.org/0000-0002-1931-6836"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kanyu Cao","raw_affiliation_strings":["Product Research and Development, ChangXin Memory Technologies, Inc.,Hefei,China,230000","Product Research and Development, ChangXin Memory Technologies, Inc., Hefei, China"],"affiliations":[{"raw_affiliation_string":"Product Research and Development, ChangXin Memory Technologies, Inc.,Hefei,China,230000","institution_ids":[]},{"raw_affiliation_string":"Product Research and Development, ChangXin Memory Technologies, Inc., Hefei, China","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100772272"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16388481,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.9329260587692261},{"id":"https://openalex.org/keywords/shallow-trench-isolation","display_name":"Shallow trench isolation","score":0.7612479329109192},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.7096202373504639},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5291889905929565},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5169838666915894},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.503119170665741},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4943571090698242},{"id":"https://openalex.org/keywords/trench","display_name":"Trench","score":0.46576547622680664},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.4639219045639038},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41345474123954773},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.33089423179626465},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.28612038493156433},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2780243456363678},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.25534966588020325},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.19997039437294006},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.1279396116733551},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.0804353654384613}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.9329260587692261},{"id":"https://openalex.org/C105066941","wikidata":"https://www.wikidata.org/wiki/Q1424524","display_name":"Shallow trench isolation","level":4,"score":0.7612479329109192},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.7096202373504639},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5291889905929565},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5169838666915894},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.503119170665741},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4943571090698242},{"id":"https://openalex.org/C155310634","wikidata":"https://www.wikidata.org/wiki/Q1852785","display_name":"Trench","level":3,"score":0.46576547622680664},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.4639219045639038},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41345474123954773},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.33089423179626465},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.28612038493156433},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2780243456363678},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.25534966588020325},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.19997039437294006},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.1279396116733551},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.0804353654384613},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon47005.2019.8983527","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon47005.2019.8983527","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 13th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.4099999964237213,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1588354251","https://openalex.org/W1978539735","https://openalex.org/W2023834387","https://openalex.org/W2033231312","https://openalex.org/W3149312527","https://openalex.org/W4239656686","https://openalex.org/W4302375843"],"related_works":["https://openalex.org/W2061776610","https://openalex.org/W2148597896","https://openalex.org/W2073935585","https://openalex.org/W2165354135","https://openalex.org/W2006928005","https://openalex.org/W1983676734","https://openalex.org/W2119814266","https://openalex.org/W1567914096","https://openalex.org/W1586836600","https://openalex.org/W2536550460"],"abstract_inverted_index":{"With":[0,21],"the":[1,9,22,25,33,47,60,68,73,81,85,92,120,131],"Dynamic":[2],"Random":[3],"Access":[4],"Memory":[5],"(DRAM)":[6],"integration":[7],"increase,":[8],"array":[10],"transistor":[11],"active":[12],"area":[13],"layout":[14],"has":[15],"arranged":[16],"in":[17,53],"6F2":[18],"mode":[19],"[1].":[20],"DRAM":[23,64],"architecture,":[24],"large":[26],"storage":[27],"node":[28],"leakage":[29,61,86,93,121],"current":[30,94,122],"caused":[31,66],"by":[32,67,102],"adjacent":[34,70],"wordline":[35],"(WL)":[36],"during":[37],"row":[38],"address":[39],"strobe":[40],"(RAS)":[41],"operating":[42],"steps":[43],"is":[44,123,134],"one":[45],"of":[46,63,116,119],"major":[48],"operation":[49],"and":[50,79,99,111,125],"reliability":[51],"concerns":[52],"circuits.":[54],"In":[55],"this":[56],"paper,":[57],"we":[58],"present":[59],"mechanisms":[62],"device":[65],"on-state":[69],"WL":[71],"on":[72,91],"shallow":[74],"trench":[75],"isolation":[76],"(STI)":[77],"region":[78],"show":[80],"methods":[82],"to":[83,129],"suppress":[84],"current.":[87],"The":[88],"proposed":[89],"methodologies":[90],"reduction":[95,115],"are":[96],"well":[97],"analyzed":[98],"verified":[100],"systematically":[101],"TCAD":[103],"(Technical":[104],"Computer":[105],"Aided":[106],"Design)":[107],"simulation.":[108],"After":[109],"dopants":[110],"architecture":[112],"optimization,":[113],"a":[114],"3.23":[117],"times":[118],"obtained":[124],"an":[126],"assessment":[127],"method":[128],"optimize":[130],"STI":[132],"depth":[133],"proposed.":[135]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
