{"id":"https://openalex.org/W3005437481","doi":"https://doi.org/10.1109/asicon47005.2019.8983513","title":"High throughput multi-code LDPC encoder for CCSDS standard","display_name":"High throughput multi-code LDPC encoder for CCSDS standard","publication_year":2019,"publication_date":"2019-10-01","ids":{"openalex":"https://openalex.org/W3005437481","doi":"https://doi.org/10.1109/asicon47005.2019.8983513","mag":"3005437481"},"language":"en","primary_location":{"id":"doi:10.1109/asicon47005.2019.8983513","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon47005.2019.8983513","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 13th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014169654","display_name":"Jinfou Xie","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jinfou Xie","raw_affiliation_strings":["State Key Lab of ASIC &#x0026; System, Fudan University,Shanghai,China","State Key Lab of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC &#x0026; System, Fudan University,Shanghai,China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102881427","display_name":"Shixian Li","orcid":"https://orcid.org/0009-0002-1160-0987"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shixian Li","raw_affiliation_strings":["State Key Lab of ASIC &#x0026; System, Fudan University,Shanghai,China","State Key Lab of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC &#x0026; System, Fudan University,Shanghai,China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101996379","display_name":"Yun Chen","orcid":"https://orcid.org/0000-0002-3736-9456"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yun Chen","raw_affiliation_strings":["State Key Lab of ASIC &#x0026; System, Fudan University,Shanghai,China","State Key Lab of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC &#x0026; System, Fudan University,Shanghai,China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101664308","display_name":"Qichen Zhang","orcid":"https://orcid.org/0000-0001-5486-5729"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qichen Zhang","raw_affiliation_strings":["State Key Lab of ASIC &#x0026; System, Fudan University,Shanghai,China","State Key Lab of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC &#x0026; System, Fudan University,Shanghai,China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100656792","display_name":"Xiaoyang Zeng","orcid":"https://orcid.org/0000-0003-3986-137X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoyang Zeng","raw_affiliation_strings":["State Key Lab of ASIC &#x0026; System, Fudan University,Shanghai,China","State Key Lab of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC &#x0026; System, Fudan University,Shanghai,China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5014169654"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.5306,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.70857312,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9857000112533569,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.8747541904449463},{"id":"https://openalex.org/keywords/low-density-parity-check-code","display_name":"Low-density parity-check code","score":0.8138699531555176},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7716213464736938},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.7010435461997986},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6530160903930664},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5383817553520203},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.524203896522522},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4830085039138794},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.474370539188385},{"id":"https://openalex.org/keywords/convolutional-code","display_name":"Convolutional code","score":0.4610862135887146},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4423831105232239},{"id":"https://openalex.org/keywords/parity-bit","display_name":"Parity bit","score":0.4403148591518402},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.35830920934677124},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3166940212249756},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.06781825423240662}],"concepts":[{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.8747541904449463},{"id":"https://openalex.org/C67692717","wikidata":"https://www.wikidata.org/wiki/Q187444","display_name":"Low-density parity-check code","level":3,"score":0.8138699531555176},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7716213464736938},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.7010435461997986},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6530160903930664},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5383817553520203},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.524203896522522},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4830085039138794},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.474370539188385},{"id":"https://openalex.org/C157899210","wikidata":"https://www.wikidata.org/wiki/Q1395022","display_name":"Convolutional code","level":3,"score":0.4610862135887146},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4423831105232239},{"id":"https://openalex.org/C131521367","wikidata":"https://www.wikidata.org/wiki/Q625502","display_name":"Parity bit","level":2,"score":0.4403148591518402},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.35830920934677124},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3166940212249756},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.06781825423240662},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon47005.2019.8983513","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon47005.2019.8983513","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 13th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.4300000071525574,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1968809050","https://openalex.org/W2120274384","https://openalex.org/W2128765501","https://openalex.org/W2593502119","https://openalex.org/W2948005629","https://openalex.org/W2979214536"],"related_works":["https://openalex.org/W2132373020","https://openalex.org/W2364622490","https://openalex.org/W2096049278","https://openalex.org/W1995335316","https://openalex.org/W2921482753","https://openalex.org/W2076999648","https://openalex.org/W2790387741","https://openalex.org/W4384074457","https://openalex.org/W2083917443","https://openalex.org/W2124455219"],"abstract_inverted_index":{"A":[0],"high":[1],"throughput":[2],"encoder":[3,45],"based":[4,65],"on":[5,66],"Recursive":[6],"Convolutional":[7],"Encoder":[8],"(RCE)":[9],"circuits":[10],"is":[11,28],"designed":[12],"for":[13],"multi-code":[14],"Quasi-Cyclic":[15],"Low-Density":[16],"Parity-Check":[17],"(QC-LDPC)":[18],"codes":[19],"of":[20,25],"CCSDS":[21],"standard.":[22],"The":[23,53],"use":[24],"system":[26],"registers":[27,74],"reduced":[29,78],"by":[30,37,79],"employing":[31],"a":[32],"parallel":[33,40],"RCE":[34,41],"circuit":[35,42],"structure;":[36],"configuring":[38],"these":[39],"structures,":[43],"the":[44,59,67,86],"can":[46,62],"support":[47],"multiple":[48],"patterns":[49],"and":[50,71,75,81],"code":[51],"rates.":[52],"FPGA":[54],"implementation":[55],"results":[56],"show":[57],"that":[58],"design":[60],"method":[61],"be":[63],"implemented":[64],"Xilinx":[68],"VC690T":[69],"chip,":[70],"its":[72],"normalized":[73],"LUTs":[76],"are":[77],"39.4%":[80],"24.4%,":[82],"respectively,":[83],"compared":[84],"with":[85],"existing":[87],"solutions.":[88]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
