{"id":"https://openalex.org/W3004503618","doi":"https://doi.org/10.1109/asicon47005.2019.8983464","title":"CoDRAM: A Novel Near Memory Computing Framework with Computational DRAM","display_name":"CoDRAM: A Novel Near Memory Computing Framework with Computational DRAM","publication_year":2019,"publication_date":"2019-10-01","ids":{"openalex":"https://openalex.org/W3004503618","doi":"https://doi.org/10.1109/asicon47005.2019.8983464","mag":"3004503618"},"language":"en","primary_location":{"id":"doi:10.1109/asicon47005.2019.8983464","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon47005.2019.8983464","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 13th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103257197","display_name":"Yu Ma","orcid":"https://orcid.org/0000-0003-4360-2098"},"institutions":[{"id":"https://openalex.org/I30809798","display_name":"ShanghaiTech University","ror":"https://ror.org/030bhh786","country_code":"CN","type":"education","lineage":["https://openalex.org/I30809798"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Yu Ma","raw_affiliation_strings":["School of Information Science and Technology, ShanghaiTech University,Shanghai,China,201210","School of Information Science and Technology, ShanghaiTech University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"School of Information Science and Technology, ShanghaiTech University,Shanghai,China,201210","institution_ids":["https://openalex.org/I30809798"]},{"raw_affiliation_string":"School of Information Science and Technology, ShanghaiTech University, Shanghai, China","institution_ids":["https://openalex.org/I30809798"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101633239","display_name":"Linfeng Zheng","orcid":"https://orcid.org/0000-0002-4029-8724"},"institutions":[{"id":"https://openalex.org/I30809798","display_name":"ShanghaiTech University","ror":"https://ror.org/030bhh786","country_code":"CN","type":"education","lineage":["https://openalex.org/I30809798"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Linfeng Zheng","raw_affiliation_strings":["School of Information Science and Technology, ShanghaiTech University,Shanghai,China,201210","School of Information Science and Technology, ShanghaiTech University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"School of Information Science and Technology, ShanghaiTech University,Shanghai,China,201210","institution_ids":["https://openalex.org/I30809798"]},{"raw_affiliation_string":"School of Information Science and Technology, ShanghaiTech University, Shanghai, China","institution_ids":["https://openalex.org/I30809798"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081772659","display_name":"Pingqiang Zhou","orcid":"https://orcid.org/0000-0001-9515-9302"},"institutions":[{"id":"https://openalex.org/I30809798","display_name":"ShanghaiTech University","ror":"https://ror.org/030bhh786","country_code":"CN","type":"education","lineage":["https://openalex.org/I30809798"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Pingqiang Zhou","raw_affiliation_strings":["School of Information Science and Technology, ShanghaiTech University,Shanghai,China,201210","School of Information Science and Technology, ShanghaiTech University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"School of Information Science and Technology, ShanghaiTech University,Shanghai,China,201210","institution_ids":["https://openalex.org/I30809798"]},{"raw_affiliation_string":"School of Information Science and Technology, ShanghaiTech University, Shanghai, China","institution_ids":["https://openalex.org/I30809798"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5103257197"],"corresponding_institution_ids":["https://openalex.org/I30809798"],"apc_list":null,"apc_paid":null,"fwci":0.1192,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.49698434,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8155584931373596},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.802003026008606},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6408896446228027},{"id":"https://openalex.org/keywords/von-neumann-architecture","display_name":"Von Neumann architecture","score":0.5316508412361145},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5142233371734619},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.49773386120796204},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.48185479640960693},{"id":"https://openalex.org/keywords/supercomputer","display_name":"Supercomputer","score":0.4297109842300415},{"id":"https://openalex.org/keywords/mode","display_name":"Mode (computer interface)","score":0.42680612206459045},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4074137806892395},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.342678964138031},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.3166426420211792},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3133733868598938},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16603395342826843},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.13050633668899536}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8155584931373596},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.802003026008606},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6408896446228027},{"id":"https://openalex.org/C80469333","wikidata":"https://www.wikidata.org/wiki/Q189088","display_name":"Von Neumann architecture","level":2,"score":0.5316508412361145},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5142233371734619},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.49773386120796204},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.48185479640960693},{"id":"https://openalex.org/C83283714","wikidata":"https://www.wikidata.org/wiki/Q121117","display_name":"Supercomputer","level":2,"score":0.4297109842300415},{"id":"https://openalex.org/C48677424","wikidata":"https://www.wikidata.org/wiki/Q6888088","display_name":"Mode (computer interface)","level":2,"score":0.42680612206459045},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4074137806892395},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.342678964138031},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.3166426420211792},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3133733868598938},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16603395342826843},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.13050633668899536},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon47005.2019.8983464","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon47005.2019.8983464","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 13th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8600000143051147}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W755906292","https://openalex.org/W1983096721","https://openalex.org/W2115125721","https://openalex.org/W2117696986","https://openalex.org/W2147657366","https://openalex.org/W2165542474","https://openalex.org/W2271878574","https://openalex.org/W2613569094","https://openalex.org/W2765234579","https://openalex.org/W2792900111","https://openalex.org/W4292169167","https://openalex.org/W6604280164"],"related_works":["https://openalex.org/W1976244802","https://openalex.org/W4293430534","https://openalex.org/W2335743642","https://openalex.org/W4297812927","https://openalex.org/W2800412005","https://openalex.org/W2122646225","https://openalex.org/W3140615508","https://openalex.org/W2029945810","https://openalex.org/W1954780666","https://openalex.org/W2216509856"],"abstract_inverted_index":{"As":[0],"CPU":[1,26],"frequency":[2],"and":[3,16,22,27,75,98,104,120,125],"computing":[4,92,107],"power":[5,23],"grow":[6],"fast,":[7],"conventional":[8,82],"Von":[9],"Neumann":[10],"architecture":[11,43,48],"is":[12,117,135],"suffering":[13],"from":[14],"more":[15,17],"severe":[18],"data":[19,54],"transfer":[20,55],"latency":[21],"consumption":[24],"between":[25],"DRAM,":[28],"known":[29],"as":[30],"memory":[31,42],"wall":[32],"problem.":[33],"In":[34],"this":[35],"paper,":[36],"we":[37],"propose":[38],"a":[39],"novel":[40],"near":[41],"based":[44],"on":[45,101],"the":[46,53,63,85,89,115,130],"H-tree":[47],"of":[49],"DRAM":[50],"to":[51],"decrease":[52],"latency.":[56],"There":[57],"are":[58],"three":[59],"work":[60],"modes":[61],"in":[62,108,112,122,132],"proposed":[64,90],"CoDRAM,":[65],"GMM":[66,133],"(General":[67],"Main":[68],"Memory":[69],"Mode),":[70],"ACM":[71,109],"(Auxiliary":[72],"Computing":[73,78],"Mode)":[74],"PCM":[76,113],"(Parallel":[77],"Mode).":[79],"Compared":[80],"with":[81],"CPU+DRAM":[83],"architecture,":[84],"experiment":[86],"shows":[87],"that":[88],"CoDRAM":[91],"framework":[93],"can":[94],"improve":[95],"about":[96,118,137],"20%":[97],"33%":[99],"performance":[100],"matrix":[102,123],"addition":[103,124],"integral":[105,126],"image":[106,127],"mode.":[110],"And":[111],"mode,":[114],"improvement":[116],"15\u00d7":[119],"3\u00d7":[121],"computing.":[128],"Meanwhile,":[129],"overhead":[131],"mode":[134],"only":[136],"1%.":[138]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}