{"id":"https://openalex.org/W2783651495","doi":"https://doi.org/10.1109/asicon.2017.8252616","title":"A programmable divider with extended division range for 24GHz FMCW frequency synthesizer","display_name":"A programmable divider with extended division range for 24GHz FMCW frequency synthesizer","publication_year":2017,"publication_date":"2017-10-01","ids":{"openalex":"https://openalex.org/W2783651495","doi":"https://doi.org/10.1109/asicon.2017.8252616","mag":"2783651495"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2017.8252616","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252616","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100528045","display_name":"Yuanyuan Xu","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuanyuan Xu","raw_affiliation_strings":["State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009189637","display_name":"Wei Li","orcid":"https://orcid.org/0000-0001-9177-4551"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wei Li","raw_affiliation_strings":["State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101964004","display_name":"Dan Wu","orcid":"https://orcid.org/0009-0001-1041-6443"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dan Wu","raw_affiliation_strings":["State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006260198","display_name":"Ning Li","orcid":"https://orcid.org/0000-0002-2428-0516"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ning Li","raw_affiliation_strings":["State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"875","last_page":"878"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9933000206947327,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/frequency-divider","display_name":"Frequency divider","score":0.8899800181388855},{"id":"https://openalex.org/keywords/current-divider","display_name":"Current divider","score":0.7871291637420654},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.6940425038337708},{"id":"https://openalex.org/keywords/division","display_name":"Division (mathematics)","score":0.6325140595436096},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5163847208023071},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.48858603835105896},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.4614042639732361},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4570979177951813},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3505818247795105},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.34745192527770996},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.1385098099708557},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08940061926841736},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.05833613872528076}],"concepts":[{"id":"https://openalex.org/C74982907","wikidata":"https://www.wikidata.org/wiki/Q1455624","display_name":"Frequency divider","level":3,"score":0.8899800181388855},{"id":"https://openalex.org/C97264828","wikidata":"https://www.wikidata.org/wiki/Q4157078","display_name":"Current divider","level":4,"score":0.7871291637420654},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.6940425038337708},{"id":"https://openalex.org/C60798267","wikidata":"https://www.wikidata.org/wiki/Q1226939","display_name":"Division (mathematics)","level":2,"score":0.6325140595436096},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5163847208023071},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.48858603835105896},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.4614042639732361},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4570979177951813},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3505818247795105},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.34745192527770996},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.1385098099708557},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08940061926841736},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.05833613872528076}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2017.8252616","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252616","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2139625690","https://openalex.org/W2410273639","https://openalex.org/W2478669779"],"related_works":["https://openalex.org/W2359366503","https://openalex.org/W2330020385","https://openalex.org/W1968508814","https://openalex.org/W2371350995","https://openalex.org/W2120564668","https://openalex.org/W1975478216","https://openalex.org/W2099990255","https://openalex.org/W2138115812","https://openalex.org/W1660461258","https://openalex.org/W2368935517"],"abstract_inverted_index":{"As":[0],"the":[1,6,11,15,41,46,50,53,66,80,99,106],"conventional":[2],"programmable":[3,22,101],"divider":[4,23,48,102],"has":[5],"division":[7,27,58,81],"failure":[8],"problem":[9,32],"at":[10,65,105],"modulus":[12,107],"extension":[13,108],"boundary,":[14],"paper":[16],"proposed":[17,69,100],"a":[18,36,74,114],"simple":[19],"and":[20,39,63,85,110],"robust":[21],"structure":[24,55,70],"with":[25,79],"extended":[26],"range":[28,82],"to":[29],"solve":[30],"this":[31],"effectively.":[33],"By":[34],"adding":[35],"reset":[37],"port":[38],"changing":[40],"polarities":[42],"of":[43,49,83],"latches":[44],"in":[45,73,88,113],"2/3":[47],"last":[51],"stage,":[52],"modified":[54],"performs":[56],"no":[57],"error":[59],"when":[60],"switched":[61],"back":[62],"forth":[64],"boundary.":[67],"The":[68,93],"is":[71,86],"applied":[72],"24GHz":[75],"FMCW":[76,115],"frequency":[77,116],"synthesizer":[78],"16~63":[84],"implemented":[87],"TSMC":[89],"65nm":[90],"CMOS":[91],"technology.":[92],"post":[94],"simulation":[95],"results":[96],"show":[97],"that":[98],"operates":[103],"properly":[104],"boundary":[109],"works":[111],"well":[112],"synthesizer.":[117]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
