{"id":"https://openalex.org/W2783614215","doi":"https://doi.org/10.1109/asicon.2017.8252607","title":"A scalable hardware architecture for multi-layer spiking neural networks","display_name":"A scalable hardware architecture for multi-layer spiking neural networks","publication_year":2017,"publication_date":"2017-10-01","ids":{"openalex":"https://openalex.org/W2783614215","doi":"https://doi.org/10.1109/asicon.2017.8252607","mag":"2783614215"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2017.8252607","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252607","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054894281","display_name":"Zhaozhong Ying","orcid":null},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhaozhong Ying","raw_affiliation_strings":["Institute of VLSI, Zhejiang University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005976848","display_name":"Chong Luo","orcid":"https://orcid.org/0000-0003-4654-5682"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chong Luo","raw_affiliation_strings":["Institute of VLSI, Zhejiang University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027236515","display_name":"Xiaolei Zhu","orcid":"https://orcid.org/0000-0001-8141-021X"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaolei Zhu","raw_affiliation_strings":["Institute of VLSI, Zhejiang University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I76130692"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I76130692"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"345","issue":null,"first_page":"839","last_page":"842"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8003596067428589},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.655704915523529},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.508655846118927},{"id":"https://openalex.org/keywords/von-neumann-architecture","display_name":"Von Neumann architecture","score":0.48021015524864197},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.47524189949035645},{"id":"https://openalex.org/keywords/spiking-neural-network","display_name":"Spiking neural network","score":0.4554767608642578},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.4203026294708252},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41662466526031494}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8003596067428589},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.655704915523529},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.508655846118927},{"id":"https://openalex.org/C80469333","wikidata":"https://www.wikidata.org/wiki/Q189088","display_name":"Von Neumann architecture","level":2,"score":0.48021015524864197},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.47524189949035645},{"id":"https://openalex.org/C11731999","wikidata":"https://www.wikidata.org/wiki/Q9067355","display_name":"Spiking neural network","level":3,"score":0.4554767608642578},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.4203026294708252},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41662466526031494},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2017.8252607","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252607","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7699999809265137}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1695065985","https://openalex.org/W1975398991","https://openalex.org/W2032832574","https://openalex.org/W2034602202","https://openalex.org/W2116859325","https://openalex.org/W2121917196","https://openalex.org/W2130360162","https://openalex.org/W2138913040","https://openalex.org/W2156640153","https://openalex.org/W2159951683","https://openalex.org/W2506323698","https://openalex.org/W3151328790"],"related_works":["https://openalex.org/W3126544799","https://openalex.org/W2389214306","https://openalex.org/W4235240664","https://openalex.org/W2965083567","https://openalex.org/W2918361313","https://openalex.org/W121182129","https://openalex.org/W2403181385","https://openalex.org/W4213353724","https://openalex.org/W4200536635","https://openalex.org/W2611005572"],"abstract_inverted_index":{"The":[0,75],"mixed-signal":[1],"spiking":[2],"neural":[3],"network":[4,31,42],"hardware":[5,24],"is":[6,26,37],"a":[7,56],"promising":[8],"solution":[9],"for":[10,40],"non-von":[11],"Neumann":[12],"computing":[13],"with":[14,98],"ultra-low":[15],"power":[16],"consumption":[17],"and":[18,33,49,61],"very":[19],"high":[20],"parallelism.":[21],"A":[22],"scalable":[23],"architecture":[25],"proposed":[27,100],"to":[28,81],"balance":[29],"the":[30,85,88,93,99],"flexibility":[32],"neuron":[34,48],"density":[35],"which":[36],"especially":[38],"suitable":[39],"multi-layer":[41,96],"implementation.":[43],"It":[44],"consists":[45],"of":[46,87,95],"analog":[47],"synapse":[50],"circuits":[51],"operating":[52],"in":[53],"sub-threshold":[54],"region,":[55],"custom":[57],"designed":[58],"SRAM":[59],"block,":[60],"synchronous":[62],"digital":[63],"I/O":[64],"control":[65],"units":[66],"based":[67],"on":[68],"Address":[69],"Event":[70],"Representation":[71],"(AER)":[72],"communication":[73],"protocol.":[74],"SPICE":[76],"simulations":[77],"have":[78],"been":[79],"performed":[80],"not":[82],"only":[83],"verify":[84],"correctness":[86],"function":[89],"but":[90],"also":[91],"show":[92],"possibility":[94],"implementation":[97],"architecture.":[101]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}