{"id":"https://openalex.org/W2784044625","doi":"https://doi.org/10.1109/asicon.2017.8252504","title":"A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area &amp; 63% standby power","display_name":"A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area &amp; 63% standby power","publication_year":2017,"publication_date":"2017-10-01","ids":{"openalex":"https://openalex.org/W2784044625","doi":"https://doi.org/10.1109/asicon.2017.8252504","mag":"2784044625"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2017.8252504","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252504","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026808971","display_name":"Fujun Bai","orcid":"https://orcid.org/0000-0002-7971-5986"},"institutions":[{"id":"https://openalex.org/I4210148388","display_name":"Xi'an UniIC Semiconductors (China)","ror":"https://ror.org/04c99ac72","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210148388"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Fujun Bai","raw_affiliation_strings":["Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China","institution_ids":["https://openalex.org/I4210148388"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110312724","display_name":"Baoyu Xiong","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148388","display_name":"Xi'an UniIC Semiconductors (China)","ror":"https://ror.org/04c99ac72","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210148388"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Baoyu Xiong","raw_affiliation_strings":["Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China","institution_ids":["https://openalex.org/I4210148388"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016098267","display_name":"Xiaofei Xue","orcid":"https://orcid.org/0000-0001-9320-0367"},"institutions":[{"id":"https://openalex.org/I4210148388","display_name":"Xi'an UniIC Semiconductors (China)","ror":"https://ror.org/04c99ac72","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210148388"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaofei Xue","raw_affiliation_strings":["Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China","institution_ids":["https://openalex.org/I4210148388"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021157866","display_name":"Weizhe Song","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148388","display_name":"Xi'an UniIC Semiconductors (China)","ror":"https://ror.org/04c99ac72","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210148388"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weizhe Song","raw_affiliation_strings":["Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China","institution_ids":["https://openalex.org/I4210148388"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027607408","display_name":"Wu Baofeng","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148388","display_name":"Xi'an UniIC Semiconductors (China)","ror":"https://ror.org/04c99ac72","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210148388"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wu Baofeng","raw_affiliation_strings":["Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China","institution_ids":["https://openalex.org/I4210148388"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082933620","display_name":"Fu Ni","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148388","display_name":"Xi'an UniIC Semiconductors (China)","ror":"https://ror.org/04c99ac72","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210148388"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ni Fu","raw_affiliation_strings":["Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China","institution_ids":["https://openalex.org/I4210148388"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009065607","display_name":"Bing Yu","orcid":"https://orcid.org/0009-0004-7297-9307"},"institutions":[{"id":"https://openalex.org/I4210148388","display_name":"Xi'an UniIC Semiconductors (China)","ror":"https://ror.org/04c99ac72","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210148388"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bing Yu","raw_affiliation_strings":["Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China","institution_ids":["https://openalex.org/I4210148388"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084918965","display_name":"Huifu Duan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148388","display_name":"Xi'an UniIC Semiconductors (China)","ror":"https://ror.org/04c99ac72","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210148388"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Huifu Duan","raw_affiliation_strings":["Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China","institution_ids":["https://openalex.org/I4210148388"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101814064","display_name":"Xiaowei Han","orcid":"https://orcid.org/0000-0002-6783-0557"},"institutions":[{"id":"https://openalex.org/I4210148388","display_name":"Xi'an UniIC Semiconductors (China)","ror":"https://ror.org/04c99ac72","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210148388"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaowei Han","raw_affiliation_strings":["Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China","institution_ids":["https://openalex.org/I4210148388"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021976120","display_name":"Alessandro Minzoni","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148388","display_name":"Xi'an UniIC Semiconductors (China)","ror":"https://ror.org/04c99ac72","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210148388"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Alessandro Minzoni","raw_affiliation_strings":["Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China","institution_ids":["https://openalex.org/I4210148388"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049081005","display_name":"Qiwei Ren","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148388","display_name":"Xi'an UniIC Semiconductors (China)","ror":"https://ror.org/04c99ac72","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210148388"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qiwei Ren","raw_affiliation_strings":["Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Xi'an Uniic Semiconductors Co. Ltd., Xi'an, China","institution_ids":["https://openalex.org/I4210148388"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":11,"corresponding_author_ids":["https://openalex.org/A5026808971"],"corresponding_institution_ids":["https://openalex.org/I4210148388"],"apc_list":null,"apc_paid":null,"fwci":0.5734,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.71047382,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"426","last_page":"428"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/standby-power","display_name":"Standby power","score":0.8143018484115601},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.762381911277771},{"id":"https://openalex.org/keywords/port","display_name":"Port (circuit theory)","score":0.7542518377304077},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5447704195976257},{"id":"https://openalex.org/keywords/leakage-power","display_name":"Leakage power","score":0.4981660842895508},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4969692528247833},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.49471232295036316},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3937121033668518},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3776334822177887},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3117868900299072},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27017414569854736},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.244358092546463},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.17014184594154358},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.0866551399230957},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.05554896593093872}],"concepts":[{"id":"https://openalex.org/C7140552","wikidata":"https://www.wikidata.org/wiki/Q1366402","display_name":"Standby power","level":3,"score":0.8143018484115601},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.762381911277771},{"id":"https://openalex.org/C32802771","wikidata":"https://www.wikidata.org/wiki/Q2443617","display_name":"Port (circuit theory)","level":2,"score":0.7542518377304077},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5447704195976257},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.4981660842895508},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4969692528247833},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.49471232295036316},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3937121033668518},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3776334822177887},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3117868900299072},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27017414569854736},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.244358092546463},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.17014184594154358},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0866551399230957},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.05554896593093872},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2017.8252504","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252504","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6600000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2109104675","https://openalex.org/W2111287256","https://openalex.org/W2136045454","https://openalex.org/W2564315205"],"related_works":["https://openalex.org/W2297319780","https://openalex.org/W2773448237","https://openalex.org/W2188598220","https://openalex.org/W2178217057","https://openalex.org/W1972800815","https://openalex.org/W1533452797","https://openalex.org/W2162271340","https://openalex.org/W3103005480","https://openalex.org/W2539500217","https://openalex.org/W4377020067"],"abstract_inverted_index":{"A":[0,17],"two-port":[1,19],"SRAM,":[2],"which":[3],"uses":[4],"a":[5,10],"single-port":[6,32],"cell":[7],"array":[8],"and":[9,44,62,69],"self-timed":[11],"write-after-read":[12],"control":[13],"scheme,":[14],"is":[15,21,39,48],"proposed.":[16],"64-kb":[18],"SRAM":[20],"fabricated":[22],"in":[23],"40nm":[24],"low-leakage":[25],"logic":[26],"process.":[27],"Taking":[28],"advantages":[29],"of":[30,36],"the":[31,34,45,57,60],"cell,":[33],"bit-density":[35],"our":[37],"design":[38],"up":[40],"to":[41],"1.94":[42],"Mb/mm2,":[43],"standby":[46,63],"power":[47,64],"48uW":[49],"at":[50,52],"1.1V":[51],"room":[53],"temperature.":[54],"Compared":[55],"with":[56],"conventional":[58],"design,":[59],"area":[61],"are":[65],"saved":[66],"by":[67],"47%":[68],"63%":[70],"respectively.":[71]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2}],"updated_date":"2026-01-13T01:12:25.745995","created_date":"2025-10-10T00:00:00"}
