{"id":"https://openalex.org/W2784016144","doi":"https://doi.org/10.1109/asicon.2017.8252498","title":"Remote embedded simulation system for SW/HW co-design based on dynamic partial reconfiguration","display_name":"Remote embedded simulation system for SW/HW co-design based on dynamic partial reconfiguration","publication_year":2017,"publication_date":"2017-10-01","ids":{"openalex":"https://openalex.org/W2784016144","doi":"https://doi.org/10.1109/asicon.2017.8252498","mag":"2784016144"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2017.8252498","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252498","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101735004","display_name":"Jiaqi Gu","orcid":"https://orcid.org/0000-0002-5304-1688"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jiaqi Gu","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088929542","display_name":"Ruoyao Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ruoyao Wang","raw_affiliation_strings":["Fudan University, Shanghai, Shanghai, CN"],"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, Shanghai, CN","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002847404","display_name":"Jian Wang","orcid":"https://orcid.org/0000-0003-4361-8946"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Wang","raw_affiliation_strings":["Fudan University, Shanghai, Shanghai, CN"],"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, Shanghai, CN","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081419061","display_name":"Jinmei Lai","orcid":"https://orcid.org/0009-0003-5238-4720"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinmei Lai","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000918972","display_name":"Qinghua Duan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Qinghua Duan","raw_affiliation_strings":["Chengdu Sino Microelectronics Technology Co. Ltd"],"affiliations":[{"raw_affiliation_string":"Chengdu Sino Microelectronics Technology Co. Ltd","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5101735004"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.24403498,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"402","last_page":"405"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10714","display_name":"Software-Defined Networks and 5G","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10714","display_name":"Software-Defined Networks and 5G","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7625612020492554},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.716781497001648},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.6994228363037109},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6182959675788879},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.454490602016449},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4488808512687683},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4388049244880676},{"id":"https://openalex.org/keywords/software-portability","display_name":"Software portability","score":0.4306633472442627},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4237458407878876},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3868032693862915},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1003064513206482}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7625612020492554},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.716781497001648},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.6994228363037109},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6182959675788879},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.454490602016449},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4488808512687683},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4388049244880676},{"id":"https://openalex.org/C63000827","wikidata":"https://www.wikidata.org/wiki/Q3080428","display_name":"Software portability","level":2,"score":0.4306633472442627},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4237458407878876},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3868032693862915},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1003064513206482},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2017.8252498","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252498","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5899999737739563,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1500819376","https://openalex.org/W1980194681","https://openalex.org/W2185877774","https://openalex.org/W2589080295","https://openalex.org/W4234837206"],"related_works":["https://openalex.org/W2808484818","https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2340647897","https://openalex.org/W4249632163","https://openalex.org/W1760305469","https://openalex.org/W2797161794","https://openalex.org/W2073075351","https://openalex.org/W2096938998"],"abstract_inverted_index":{"Projects":[0],"involving":[1],"both":[2],"software":[3],"design":[4,7],"and":[5,16,26,47,78,86,94,103,184,191],"hardware":[6],"are":[8],"usually":[9],"retarded":[10],"by":[11],"expensive":[12],"equipments,":[13],"complex":[14],"simulation":[15,40,112],"challenging":[17],"modification.":[18],"In":[19,136],"order":[20,137],"to":[21,42,58,124,138,174],"retrench":[22],"the":[23,56,108,181,209],"designers'":[24],"time":[25],"economic":[27],"costs":[28],"in":[29],"SW/HW":[30,50,171,195],"(Software/Hardware)":[31],"co-design":[32,51,172,196],"simulation,":[33,104],"this":[34,140],"paper":[35],"demonstrates":[36,180],"a":[37,64,118,130,144,147,163,213],"remote":[38,189],"embedded":[39,111],"system":[41,70,74],"help":[43],"multiple":[44,97],"users":[45,117],"manage":[46],"simulate":[48],"their":[49],"projects":[52,197],"remotely":[53],"while":[54],"scheduling":[55],"access":[57],"on-chip":[59],"FPGA":[60,101],"resources.":[61],"We":[62,166],"built":[63],"small-scale,":[65],"high-concurrent":[66],"multiuser":[67,84],"management":[68],"service":[69],"on":[71,146,159,162],"board.":[72],"The":[73,177,206],"offers":[75],"TCP/IP":[76],"connection":[77],"transmission,":[79],"flexible":[80],"Wi-Fi":[81],"network,":[82],"secure":[83],"information":[85],"files":[87],"management,":[88],"real-time":[89],"task":[90],"progress":[91],"notification,":[92],"compilation":[93],"execution":[95],"of":[96,212],"programming":[98],"languages,":[99],"run-time":[100],"configuration":[102],"which":[105,128],"considerably":[106],"augments":[107],"exploitability":[109],"for":[110,208],"service.":[113],"Meanwhile,":[114],"we":[115,142],"offer":[116],"supporting":[119],"PC":[120],"(Personal":[121],"Computer)":[122],"application":[123],"attain":[125],"pertinent":[126],"features,":[127],"has":[129],"multithreading":[131],"GUI":[132],"(Graphical":[133],"User":[134],"Interface).":[135],"verify":[139],"design,":[141],"deploy":[143],"prototype":[145],"Xilinx":[148],"Zynq":[149],"<sup":[150],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[151],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">\u2122</sup>":[152],"-7000":[153],"AP":[154],"(All":[155],"Programmable)":[156],"SoC":[157],"(System":[158],"Chips)":[160],"Z-7010":[161],"ZYBO":[164],"Board.":[165],"apply":[167],"an":[168],"image":[169],"processing":[170],"project":[173],"our":[175],"prototype.":[176],"experiment":[178],"result":[179],"system's":[182],"portability":[183],"efficacy":[185],"when":[186,193],"dealing":[187],"with":[188],"access,":[190],"flexibility":[192],"simulating":[194],"through":[198],"PR":[199],"(Partial":[200],"Reconfiguration)":[201],"technique":[202],"within":[203],"reasonable":[204],"latency.":[205],"latency":[207],"end-to-end":[210],"reconfiguration":[211],"306.60KB":[214],"partial":[215],"bitfile":[216],"is":[217],"8.819ms.":[218]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}