{"id":"https://openalex.org/W2783276420","doi":"https://doi.org/10.1109/asicon.2017.8252484","title":"A method to speed up VLSI hierarchical physical design in floorplanning","display_name":"A method to speed up VLSI hierarchical physical design in floorplanning","publication_year":2017,"publication_date":"2017-10-01","ids":{"openalex":"https://openalex.org/W2783276420","doi":"https://doi.org/10.1109/asicon.2017.8252484","mag":"2783276420"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2017.8252484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100966377","display_name":"Yanling Zhou","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yanling Zhou","raw_affiliation_strings":["School of Software&Microelectronics, Peking University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Software&Microelectronics, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063890395","display_name":"Yunyao Yan","orcid":"https://orcid.org/0009-0005-0830-1830"},"institutions":[{"id":"https://openalex.org/I21193070","display_name":"Beijing Jiaotong University","ror":"https://ror.org/01yj56c84","country_code":"CN","type":"education","lineage":["https://openalex.org/I21193070"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yunyao Yan","raw_affiliation_strings":["Beijing Jiaotong University, Beijing, Beijing, CN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Beijing Jiaotong University, Beijing, Beijing, CN","institution_ids":["https://openalex.org/I21193070"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5086759697","display_name":"Wei Yan","orcid":"https://orcid.org/0000-0002-0745-9514"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]},{"id":"https://openalex.org/I21193070","display_name":"Beijing Jiaotong University","ror":"https://ror.org/01yj56c84","country_code":"CN","type":"education","lineage":["https://openalex.org/I21193070"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wei Yan","raw_affiliation_strings":["School of Electronic and Information Engineering, Beijing JiaoTong University, Beijing, China","School of Software&Microelectronics, Peking University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronic and Information Engineering, Beijing JiaoTong University, Beijing, China","institution_ids":["https://openalex.org/I21193070"]},{"raw_affiliation_string":"School of Software&Microelectronics, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"347","last_page":"350"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9692094922065735},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8660369515419006},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.807949423789978},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.7470422387123108},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7072779536247253},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5592367053031921},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.49694398045539856},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.42282581329345703},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40489596128463745},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33487170934677124},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.24214980006217957}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9692094922065735},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8660369515419006},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.807949423789978},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.7470422387123108},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7072779536247253},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5592367053031921},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49694398045539856},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.42282581329345703},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40489596128463745},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33487170934677124},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.24214980006217957}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2017.8252484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","score":0.4099999964237213,"display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1773350357","https://openalex.org/W1985714852","https://openalex.org/W1995846884","https://openalex.org/W2008011539","https://openalex.org/W2043725682","https://openalex.org/W2094042791","https://openalex.org/W2105761964","https://openalex.org/W2110514755","https://openalex.org/W2114772983","https://openalex.org/W2137494283","https://openalex.org/W4240309467","https://openalex.org/W4256007160","https://openalex.org/W6649352999","https://openalex.org/W6674301526"],"related_works":["https://openalex.org/W2350308400","https://openalex.org/W4245336546","https://openalex.org/W2123076670","https://openalex.org/W2030503305","https://openalex.org/W2038511870","https://openalex.org/W2543290882","https://openalex.org/W2126475478","https://openalex.org/W4253195573","https://openalex.org/W2075511834","https://openalex.org/W2781601456"],"abstract_inverted_index":{"With":[0],"the":[1,42,94,116],"rapid":[2],"increase":[3],"in":[4,34,53,132],"size":[5],"and":[6,16,72,83,125],"complexity":[7],"of":[8,19,111],"VLSI,":[9],"it":[10,99],"is":[11],"hard":[12],"to":[13,91],"meet":[14],"speed":[15],"quality":[17,103],"requirement":[18],"IC":[20],"physical":[21,38,135],"design.":[22],"In":[23],"this":[24,87],"paper,":[25],"we":[26],"present":[27],"an":[28],"efficient":[29],"model":[30,48],"for":[31],"quick":[32],"floorplanning":[33],"VLSI":[35,133],"top-down":[36],"hierarchical":[37,134],"design":[39,77,102,107],"flow":[40],"using":[41],"Active-Logic":[43],"Reduction":[44],"Technology.":[45],"The":[46,109],"simplified":[47],"replaces":[49],"some":[50],"original":[51],"modules":[52],"netlist":[54],"file":[55],"with":[56,86],"filling":[57],"units":[58,71],"which":[59],"have":[60],"no":[61],"logical":[62,70],"connections.":[63],"This":[64],"method":[65,117],"can":[66,100,118],"effectively":[67],"reduce":[68,120],"internal":[69],"quickly":[73,92],"predict":[74],"if":[75],"chip":[76],"achieves":[78],"timing":[79],"closure":[80],"after":[81],"top":[82],"blocks":[84],"implementation":[85],"floorplan":[88],"so":[89],"as":[90],"judge":[93],"floorplan's":[95],"quality.":[96],"Most":[97],"importantly,":[98],"maintain":[101],"while":[104],"speeding":[105],"up":[106],"flow.":[108],"results":[110],"six":[112],"experiments":[113],"show":[114],"that":[115],"drastically":[119],"runtime":[121],"by":[122,127],"6.2":[123],"times":[124,129],"memory":[126],"2.8":[128],"on":[130],"average":[131],"designs.":[136]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":5},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}