{"id":"https://openalex.org/W2783300758","doi":"https://doi.org/10.1109/asicon.2017.8252465","title":"Memristor-based material implication logic design for full adders","display_name":"Memristor-based material implication logic design for full adders","publication_year":2017,"publication_date":"2017-10-01","ids":{"openalex":"https://openalex.org/W2783300758","doi":"https://doi.org/10.1109/asicon.2017.8252465","mag":"2783300758"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2017.8252465","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252465","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100643016","display_name":"Mengting Li","orcid":"https://orcid.org/0000-0002-2895-7010"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Mengting Li","raw_affiliation_strings":["Department of Electronic Sci. & Tech, University of Science and Technology of China, Hefei, China"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Sci. & Tech, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101982532","display_name":"Wenhao Sun","orcid":"https://orcid.org/0000-0001-8190-0120"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wenhao Sun","raw_affiliation_strings":["Department of Electronic Sci. & Tech, University of Science and Technology of China, Hefei, China"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Sci. & Tech, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000480948","display_name":"Zhimin Lu","orcid":"https://orcid.org/0000-0002-2859-2736"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhimin Lu","raw_affiliation_strings":["Department of Electronic Sci. & Tech, University of Science and Technology of China, Hefei, China"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Sci. & Tech, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100423614","display_name":"Song Chen","orcid":"https://orcid.org/0000-0003-0341-3428"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Song Chen","raw_affiliation_strings":["Department of Electronic Sci. & Tech, University of Science and Technology of China, Hefei, China"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Sci. & Tech, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101689435","display_name":"Feng Wu","orcid":"https://orcid.org/0000-0003-4665-0124"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Feng Wu","raw_affiliation_strings":["Department of Electronic Sci. & Tech, University of Science and Technology of China, Hefei, China"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Sci. & Tech, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5100643016"],"corresponding_institution_ids":["https://openalex.org/I126520041"],"apc_list":null,"apc_paid":null,"fwci":0.1433,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.54114666,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"271","last_page":"274"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9205635190010071},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.9191932678222656},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6754498481750488},{"id":"https://openalex.org/keywords/memistor","display_name":"Memistor","score":0.6128827333450317},{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.5815602540969849},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5778464674949646},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5423816442489624},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4470404088497162},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4302127957344055},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.4274784028530121},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.40707603096961975},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3985429108142853},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35267844796180725},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.32753974199295044},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1953130066394806},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16151437163352966},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.14556393027305603},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1407659351825714},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1380448043346405},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.05904972553253174}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9205635190010071},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.9191932678222656},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6754498481750488},{"id":"https://openalex.org/C1895703","wikidata":"https://www.wikidata.org/wiki/Q6034938","display_name":"Memistor","level":4,"score":0.6128827333450317},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.5815602540969849},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5778464674949646},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5423816442489624},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4470404088497162},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4302127957344055},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.4274784028530121},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40707603096961975},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3985429108142853},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35267844796180725},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.32753974199295044},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1953130066394806},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16151437163352966},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.14556393027305603},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1407659351825714},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1380448043346405},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.05904972553253174},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2017.8252465","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252465","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.47999998927116394,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1986623396","https://openalex.org/W2004782555","https://openalex.org/W2018774711","https://openalex.org/W2025674646","https://openalex.org/W2064632620","https://openalex.org/W2066280488","https://openalex.org/W2074865640","https://openalex.org/W2081729575","https://openalex.org/W2112181056","https://openalex.org/W2162651880","https://openalex.org/W2248506981","https://openalex.org/W2914596496","https://openalex.org/W2952846446","https://openalex.org/W6646974671"],"related_works":["https://openalex.org/W3170109256","https://openalex.org/W2171130799","https://openalex.org/W2015477599","https://openalex.org/W3164474614","https://openalex.org/W4253441086","https://openalex.org/W2548135880","https://openalex.org/W2516929886","https://openalex.org/W3177379469","https://openalex.org/W2005875039","https://openalex.org/W2942778963"],"abstract_inverted_index":{"The":[0],"memristor":[1,19,124],"has":[2,20],"the":[3,13,18,26,33,54,57,80,119,123],"abilities":[4],"of":[5,28,60,82],"storage":[6],"and":[7,9,30,79,85,104,137],"computation,":[8],"is":[10,68],"compatiable":[11],"with":[12,53,64,91],"standard":[14],"CMOS":[15],"technology.":[16],"Consequently,":[17],"been":[21],"thought":[22],"to":[23,72,101,107],"potentially":[24],"break":[25],"bottlenecks":[27],"memory":[29],"power":[31],"in":[32,88],"traditional":[34],"computer":[35],"architecture.":[36],"In":[37],"this":[38],"work,":[39],"we":[40,111],"present":[41,112],"optimized":[42],"full":[43,62,89],"adders":[44,90],"using":[45,75],"memristor-based":[46],"material":[47],"implication":[48],"(IMPLY)":[49],"logic":[50,121],"operation.":[51],"Compared":[52],"latest":[55],"works,":[56],"execution":[58,83,142],"steps":[59,84,143],"N-bit":[61,146],"adder":[63,116],"a":[65,92,113],"serial":[66],"structure":[67,94],"reduced":[69,96],"from":[70,97,105],"23N":[71],"16N":[73],"while":[74],"one":[76],"less":[77],"memristor,":[78],"number":[81],"memristors":[86,136],"used":[87],"parallel":[93],"are":[95],"5N":[98],"+":[99,130,134],"18":[100],"3N":[102,140],"+9":[103],"9N":[106],"8N,":[108],"respectively.":[109],"Additionally,":[110],"look-ahead":[114],"carry":[115],"based":[117],"on":[118,122],"IMPLY":[120],"crossbar":[125],"structure,":[126],"which":[127],"consumes":[128],"(3N":[129],"8)":[131],"\u00d7":[132],"(N":[133],"3)":[135],"needs":[138],"only":[139],"+15":[141],"for":[144],"an":[145],"addition.":[147]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}