{"id":"https://openalex.org/W2783877103","doi":"https://doi.org/10.1109/asicon.2017.8252453","title":"Heterogeneous computing for CNN","display_name":"Heterogeneous computing for CNN","publication_year":2017,"publication_date":"2017-10-01","ids":{"openalex":"https://openalex.org/W2783877103","doi":"https://doi.org/10.1109/asicon.2017.8252453","mag":"2783877103"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2017.8252453","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252453","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022287949","display_name":"Huizi Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Huizi Zhang","raw_affiliation_strings":["School of Microelectronics, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101530541","display_name":"Chang Wu","orcid":"https://orcid.org/0000-0003-2590-6338"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]},{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chang Wu","raw_affiliation_strings":["School of Microelectronics, Fudan University, Shanghai, China","State Key Laboratory of ASIC and Systems"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and Systems","institution_ids":["https://openalex.org/I4391767673"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072904902","display_name":"Xiao Hu","orcid":"https://orcid.org/0000-0001-7668-4689"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Xiao Hu","raw_affiliation_strings":["Intel Asia-Pacific Research&Development, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Intel Asia-Pacific Research&Development, Shanghai, China","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5022287949"],"corresponding_institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4210132426"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.20477195,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"11","issue":null,"first_page":"226","last_page":"229"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10057","display_name":"Face and Expression Recognition","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8716593980789185},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.8101363182067871},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7286937832832336},{"id":"https://openalex.org/keywords/symmetric-multiprocessor-system","display_name":"Symmetric multiprocessor system","score":0.653330385684967},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6511809229850769},{"id":"https://openalex.org/keywords/convolutional-neural-network","display_name":"Convolutional neural network","score":0.6329367160797119},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.6208290457725525},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.6147059798240662},{"id":"https://openalex.org/keywords/partition","display_name":"Partition (number theory)","score":0.5409942269325256},{"id":"https://openalex.org/keywords/cpu-shielding","display_name":"CPU shielding","score":0.43153390288352966},{"id":"https://openalex.org/keywords/general-purpose-computing-on-graphics-processing-units","display_name":"General-purpose computing on graphics processing units","score":0.4161127209663391},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34486931562423706},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.26661956310272217},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.15865975618362427},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.15449044108390808},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1439017951488495},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1291508674621582},{"id":"https://openalex.org/keywords/graphics","display_name":"Graphics","score":0.1079927384853363}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8716593980789185},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.8101363182067871},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7286937832832336},{"id":"https://openalex.org/C172430144","wikidata":"https://www.wikidata.org/wiki/Q17111997","display_name":"Symmetric multiprocessor system","level":2,"score":0.653330385684967},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6511809229850769},{"id":"https://openalex.org/C81363708","wikidata":"https://www.wikidata.org/wiki/Q17084460","display_name":"Convolutional neural network","level":2,"score":0.6329367160797119},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.6208290457725525},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.6147059798240662},{"id":"https://openalex.org/C42812","wikidata":"https://www.wikidata.org/wiki/Q1082910","display_name":"Partition (number theory)","level":2,"score":0.5409942269325256},{"id":"https://openalex.org/C180613757","wikidata":"https://www.wikidata.org/wiki/Q5013757","display_name":"CPU shielding","level":3,"score":0.43153390288352966},{"id":"https://openalex.org/C50630238","wikidata":"https://www.wikidata.org/wiki/Q971505","display_name":"General-purpose computing on graphics processing units","level":3,"score":0.4161127209663391},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34486931562423706},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.26661956310272217},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.15865975618362427},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.15449044108390808},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1439017951488495},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1291508674621582},{"id":"https://openalex.org/C21442007","wikidata":"https://www.wikidata.org/wiki/Q1027879","display_name":"Graphics","level":2,"score":0.1079927384853363},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2017.8252453","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252453","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6100000143051147,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1580267013","https://openalex.org/W2018034355","https://openalex.org/W2473914111","https://openalex.org/W2519985940"],"related_works":["https://openalex.org/W2387982802","https://openalex.org/W1896942098","https://openalex.org/W1991061790","https://openalex.org/W2088078730","https://openalex.org/W2400763249","https://openalex.org/W2350289853","https://openalex.org/W2391126280","https://openalex.org/W2061938028","https://openalex.org/W2330590072","https://openalex.org/W2001170981"],"abstract_inverted_index":{"As":[0],"a":[1,49,108],"typical":[2],"machine":[3],"learning":[4],"algorithm,":[5],"convolutional":[6],"neural":[7],"network":[8],"(CNN)":[9],"has":[10],"drawn":[11],"great":[12],"interests":[13],"in":[14],"academic":[15],"research":[16],"and":[17,71,89,121,126],"industrial":[18],"applications.":[19],"However,":[20],"traditional":[21],"CPU":[22,41,88,101],"can":[23,95],"no":[24],"longer":[25],"meet":[26],"the":[27,84],"computation":[28,53,98],"requirement":[29],"of":[30,65,87,92],"CNN":[31,66],"due":[32],"to":[33,47,112],"CPU's":[34],"sequential":[35],"computing":[36,39,69,91],"nature.":[37],"Heterogeneous":[38],"combines":[40],"together":[42],"with":[43],"GPGPU":[44],"or":[45,102],"FPGAs":[46],"form":[48],"much":[50],"more":[51,74],"powerful":[52],"platform.":[54],"In":[55],"this":[56],"paper,":[57],"we":[58],"present":[59],"our":[60],"study":[61,80],"on":[62,67],"an":[63,114],"implementation":[64,118,123],"heterogeneous":[68,132],"systems,":[70],"it":[72],"shows":[73,81],"than":[75,100],"3x":[76],"runtime":[77],"speedup.":[78],"Our":[79],"systematically":[82],"combine":[83],"high":[85],"speed":[86,99],"parallel":[90],"FPGA,":[93],"one":[94],"achieve":[96],"better":[97],"FPGA":[103],"alone.":[104],"We":[105],"also":[106],"propose":[107],"systematic":[109],"analysis":[110],"method":[111],"partition":[113],"algorithm":[115],"into":[116],"software":[117],"(on":[119,124],"CPU)":[120],"hardware":[122],"FPGA)":[125],"derive":[127],"near":[128],"optimal":[129],"solution":[130],"for":[131],"computing.":[133]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}