{"id":"https://openalex.org/W2783547720","doi":"https://doi.org/10.1109/asicon.2017.8252414","title":"A new error masking flip-flop with one cycle correction penalty","display_name":"A new error masking flip-flop with one cycle correction penalty","publication_year":2017,"publication_date":"2017-10-01","ids":{"openalex":"https://openalex.org/W2783547720","doi":"https://doi.org/10.1109/asicon.2017.8252414","mag":"2783547720"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2017.8252414","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252414","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004555943","display_name":"Zhenqiang Yong","orcid":"https://orcid.org/0000-0003-2121-561X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhenqiang Yong","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046536624","display_name":"Xiaoyan Xiang","orcid":"https://orcid.org/0000-0002-5602-2749"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoyan Xiang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100418370","display_name":"Chen Chen","orcid":"https://orcid.org/0000-0001-7587-3314"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chen Chen","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022767878","display_name":"Jianyi Meng","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianyi Meng","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.24012337,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"72","last_page":"75"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.8588334321975708},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7281315922737122},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.668605387210846},{"id":"https://openalex.org/keywords/masking","display_name":"Masking (illustration)","score":0.637141227722168},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.6182916760444641},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5989755392074585},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5802196264266968},{"id":"https://openalex.org/keywords/margin","display_name":"Margin (machine learning)","score":0.492255836725235},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4882092773914337},{"id":"https://openalex.org/keywords/resilience","display_name":"Resilience (materials science)","score":0.4805205762386322},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4240399897098541},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2292954921722412},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.22294804453849792},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15512710809707642},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.09445887804031372}],"concepts":[{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.8588334321975708},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7281315922737122},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.668605387210846},{"id":"https://openalex.org/C2777402240","wikidata":"https://www.wikidata.org/wiki/Q6783436","display_name":"Masking (illustration)","level":2,"score":0.637141227722168},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.6182916760444641},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5989755392074585},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5802196264266968},{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.492255836725235},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4882092773914337},{"id":"https://openalex.org/C2779585090","wikidata":"https://www.wikidata.org/wiki/Q3457762","display_name":"Resilience (materials science)","level":2,"score":0.4805205762386322},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4240399897098541},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2292954921722412},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.22294804453849792},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15512710809707642},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.09445887804031372},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2017.8252414","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252414","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2783525109","https://openalex.org/W4230846245","https://openalex.org/W2109802623","https://openalex.org/W2763646728","https://openalex.org/W4206433830","https://openalex.org/W4300456897","https://openalex.org/W2611474147","https://openalex.org/W4362681893","https://openalex.org/W3108715624","https://openalex.org/W2168373109"],"abstract_inverted_index":{"The":[0],"dynamic":[1],"timing":[2,22,29],"variation":[3,25],"under":[4],"the":[5,21,72,78,84,100],"nanometer":[6],"CMOS":[7,96],"technology":[8],"becomes":[9],"a":[10,42,57,88],"major":[11],"problem":[12],"for":[13,24],"IC":[14],"design.":[15],"A":[16],"typical":[17],"way":[18],"to":[19,99],"eliminate":[20],"margin":[23],"is":[26,63,92],"using":[27],"on-line":[28],"Error":[30,59],"Detection":[31],"and":[32,48,109,123],"Correction":[33],"(EDC)":[34],"technique.":[35],"However,":[36],"most":[37],"of":[38,45,86],"EDC":[39],"techniques":[40],"require":[41],"large":[43],"amount":[44],"transistor":[46,80],"count":[47],"result":[49],"in":[50,94],"area":[51],"overhead.":[52],"To":[53,82],"address":[54],"this":[55],"issue,":[56],"new":[58],"Masking":[60],"Flip-Flop":[61],"(EMFF)":[62],"proposed.":[64],"Compared":[65],"with":[66,77,104,114,118],"other":[67],"previous":[68],"error":[69],"resilience":[70],"cells,":[71],"proposed":[73],"EMFF":[74,105,119],"achieves":[75,120],"self-correction":[76],"least":[79],"counts.":[81],"study":[83],"benefits":[85],"EMFF,":[87],"3-stages":[89],"embedded":[90],"CPU":[91],"implemented":[93],"40-nm":[95],"technology.":[97],"According":[98],"experimental":[101],"results,":[102],"design":[103,117],"can":[106],"tolerate":[107],"frequency":[108],"voltage":[110],"variations.":[111],"Moreover,":[112],"compared":[113],"margined":[115],"baseline,":[116],"3.3\u00d7":[121],"performance":[122],"1.6\u00d7":[124],"energy-efficiency":[125],"at":[126],"0.9":[127],"V":[128],"supply":[129],"voltage.":[130]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}