{"id":"https://openalex.org/W2784140239","doi":"https://doi.org/10.1109/asicon.2017.8252405","title":"Auxiliary testability design schemes for CMOS DACs with ultrahigh sampling rates","display_name":"Auxiliary testability design schemes for CMOS DACs with ultrahigh sampling rates","publication_year":2017,"publication_date":"2017-10-01","ids":{"openalex":"https://openalex.org/W2784140239","doi":"https://doi.org/10.1109/asicon.2017.8252405","mag":"2784140239"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2017.8252405","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252405","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101525541","display_name":"Bao Li","orcid":"https://orcid.org/0000-0002-8944-7970"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bao Li","raw_affiliation_strings":["School of Electronics Engineering and Computer Science, Peking University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronics Engineering and Computer Science, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101855662","display_name":"Long Zhao","orcid":"https://orcid.org/0000-0003-0590-2938"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Long Zhao","raw_affiliation_strings":["School of Electronics Engineering and Computer Science, Peking University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronics Engineering and Computer Science, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068200524","display_name":"Yuhua Cheng","orcid":"https://orcid.org/0000-0001-8704-5241"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yu-Hua Cheng","raw_affiliation_strings":["School of Electronics Engineering and Computer Science, Peking University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronics Engineering and Computer Science, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I20231570"],"apc_list":null,"apc_paid":null,"fwci":0.1902,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.42834856,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"36","last_page":"39"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/gigabit","display_name":"Gigabit","score":0.798535943031311},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7198519706726074},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.688834011554718},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.665401816368103},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6645030975341797},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6120932102203369},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5017204284667969},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36837154626846313},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24739602208137512},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09607738256454468}],"concepts":[{"id":"https://openalex.org/C21922175","wikidata":"https://www.wikidata.org/wiki/Q3105497","display_name":"Gigabit","level":2,"score":0.798535943031311},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7198519706726074},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.688834011554718},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.665401816368103},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6645030975341797},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6120932102203369},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5017204284667969},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36837154626846313},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24739602208137512},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09607738256454468},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2017.8252405","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2017.8252405","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 12th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6700000166893005}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2009169305","https://openalex.org/W2131853386","https://openalex.org/W2166417864","https://openalex.org/W2185377952","https://openalex.org/W4210246447"],"related_works":["https://openalex.org/W2393524141","https://openalex.org/W2365130684","https://openalex.org/W2370255574","https://openalex.org/W2169676947","https://openalex.org/W2906367154","https://openalex.org/W2106502108","https://openalex.org/W2783560053","https://openalex.org/W2098899017","https://openalex.org/W2381807899","https://openalex.org/W2382598150"],"abstract_inverted_index":{"Current-steering":[0],"CMOS":[1],"digital-to-analog":[2],"converters":[3],"(DACs)":[4],"are":[5,85],"widely":[6],"used":[7],"ultrahigh-speed":[8],"systems.":[9],"However,":[10],"two":[11,53],"main":[12],"testability":[13],"problems":[14],"arise":[15],"with":[16,80],"sampling":[17],"rates":[18,68],"above":[19,48,69],"tens":[20],"of":[21,25,94,113],"gigabits:":[22],"the":[23,36,43,50,72,75,88,99,117],"difficulty":[24],"generating":[26],"input":[27,65],"digital":[28,66],"testing":[29],"patterns":[30],"at":[31],"gigabit":[32,106],"data":[33,67,107],"rates,":[34],"and":[35,71],"restricted":[37],"analog":[38],"output":[39,76],"bandwidth":[40,77,119,128],"due":[41],"to":[42],"parasitic":[44],"capacitance.":[45],"To":[46],"overcome":[47],"difficulties,":[49],"paper":[51],"presents":[52],"auxiliary":[54,100],"design":[55],"schemes.":[56,90],"One":[57],"is":[58,74],"on-chip":[59,101],"register-based":[60],"memory":[61,102],"for":[62],"providing":[63],"high":[64],"Gb/s,":[70],"other":[73],"enhancement":[78],"technique":[79],"passive":[81],"inductors.":[82],"Two":[83],"chips":[84],"designed":[86],"employing":[87],"presented":[89,118],"The":[91,109],"measurement":[92],"results":[93,112],"6.4GS/s":[95],"DAC":[96,115],"prototype":[97],"show":[98],"can":[103],"generate":[104],"parallel":[105],"properly.":[108],"post-layout":[110],"simulation":[111],"20GS/s":[114],"indicate":[116],"extension":[120],"scheme":[121],"achieves":[122],">12GHz":[123],"-3dB":[124],"bandwidth,":[125],"nearly":[126],"50%":[127],"improvement.":[129]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
