{"id":"https://openalex.org/W2479133589","doi":"https://doi.org/10.1109/asicon.2015.7517211","title":"Study and implementation of cluster hierarchical memory system of multicore cryptographic processor","display_name":"Study and implementation of cluster hierarchical memory system of multicore cryptographic processor","publication_year":2015,"publication_date":"2015-11-01","ids":{"openalex":"https://openalex.org/W2479133589","doi":"https://doi.org/10.1109/asicon.2015.7517211","mag":"2479133589"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2015.7517211","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2015.7517211","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 11th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100374862","display_name":"Junwei Li","orcid":"https://orcid.org/0000-0001-9500-9005"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Junwei Li","raw_affiliation_strings":["Department of Microelectronics, Zhengzhou Institute of Information Science and Technology, Zhengzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, Zhengzhou Institute of Information Science and Technology, Zhengzhou, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103036777","display_name":"Zibin Dai","orcid":"https://orcid.org/0000-0003-0359-8434"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zibin Dai","raw_affiliation_strings":["Department of Microelectronics, Zhengzhou Institute of Information Science and Technology, Zhengzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, Zhengzhou Institute of Information Science and Technology, Zhengzhou, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100318328","display_name":"Wei Li","orcid":"https://orcid.org/0000-0002-9637-2882"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wei Li","raw_affiliation_strings":["Department of Microelectronics, Zhengzhou Institute of Information Science and Technology, Zhengzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, Zhengzhou Institute of Information Science and Technology, Zhengzhou, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100357719","display_name":"Tao Chen","orcid":"https://orcid.org/0000-0001-9704-9545"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tao Chen","raw_affiliation_strings":["Department of Microelectronics, Zhengzhou Institute of Information Science and Technology, Zhengzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, Zhengzhou Institute of Information Science and Technology, Zhengzhou, China","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100949488","display_name":"Yufei Zhu","orcid":"https://orcid.org/0009-0001-7092-7608"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yufei Zhu","raw_affiliation_strings":["Department of Microelectronics, Zhengzhou Institute of Information Science and Technology, Zhengzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, Zhengzhou Institute of Information Science and Technology, Zhengzhou, China","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.29321448,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"36","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9876999855041504,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9876999855041504,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9648000001907349,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9476000070571899,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8131817579269409},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.609365701675415},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.594355583190918},{"id":"https://openalex.org/keywords/cryptographic-primitive","display_name":"Cryptographic primitive","score":0.547508955001831},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4843505620956421},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4588163495063782},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.4373752176761627},{"id":"https://openalex.org/keywords/cryptographic-protocol","display_name":"Cryptographic protocol","score":0.4237218499183655},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.31566286087036133},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2287587821483612},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.1822395622730255},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.08121705055236816}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8131817579269409},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.609365701675415},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.594355583190918},{"id":"https://openalex.org/C15927051","wikidata":"https://www.wikidata.org/wiki/Q246593","display_name":"Cryptographic primitive","level":4,"score":0.547508955001831},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4843505620956421},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4588163495063782},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.4373752176761627},{"id":"https://openalex.org/C33884865","wikidata":"https://www.wikidata.org/wiki/Q1254335","display_name":"Cryptographic protocol","level":3,"score":0.4237218499183655},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.31566286087036133},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2287587821483612},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.1822395622730255},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.08121705055236816}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2015.7517211","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2015.7517211","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 11th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6800000071525574}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1987763247","https://openalex.org/W2017087955","https://openalex.org/W2381754516","https://openalex.org/W2386573203","https://openalex.org/W6654688908"],"related_works":["https://openalex.org/W2904818008","https://openalex.org/W2904314268","https://openalex.org/W57958781","https://openalex.org/W2349791858","https://openalex.org/W254684032","https://openalex.org/W1578381328","https://openalex.org/W120214571","https://openalex.org/W1848192231","https://openalex.org/W1824582190","https://openalex.org/W4291801887"],"abstract_inverted_index":{"In":[0],"order":[1],"to":[2,25],"improve":[3],"data":[4],"bandwidth":[5],"and":[6,35,52,64],"enhance":[7],"memory":[8,33,37,54,61],"access":[9,55,62],"efficiency":[10],"in":[11],"multi-core":[12],"cryptographic":[13,28,48],"processor,":[14],"a":[15],"kind":[16],"of":[17,27],"Cluster":[18],"Hierarchical":[19],"Memory":[20],"System(CHMS)":[21],"is":[22],"proposed.":[23],"According":[24],"characteristic":[26],"algorithms/protocols":[29],"parallel":[30],"processing,":[31],"shared":[32],"unit":[34,38],"stream":[36],"are":[39],"designed.":[40],"Result":[41],"shows":[42],"that,":[43],"CHMS":[44,57],"can":[45],"make":[46],"related":[47],"core":[49],"more":[50],"tighter":[51],"reduce":[53],"conflicts.":[56],"also":[58],"has":[59],"fewer":[60],"latency":[63],"higher":[65],"efficiency.":[66]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}