{"id":"https://openalex.org/W2506513733","doi":"https://doi.org/10.1109/asicon.2015.7517162","title":"An iterative synthesis method for timing-driven design","display_name":"An iterative synthesis method for timing-driven design","publication_year":2015,"publication_date":"2015-11-01","ids":{"openalex":"https://openalex.org/W2506513733","doi":"https://doi.org/10.1109/asicon.2015.7517162","mag":"2506513733"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2015.7517162","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2015.7517162","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 11th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007296623","display_name":"Jie Zhang","orcid":"https://orcid.org/0000-0002-8073-2118"},"institutions":[{"id":"https://openalex.org/I4210100517","display_name":"Hefei Cement Research Design Institute","ror":"https://ror.org/00kaycc68","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210100517"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhang Jie","raw_affiliation_strings":["IC Design Center, CETC No.38 Research Institute, Hefei, China"],"affiliations":[{"raw_affiliation_string":"IC Design Center, CETC No.38 Research Institute, Hefei, China","institution_ids":["https://openalex.org/I4210100517"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103657859","display_name":"Lin Jin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210100517","display_name":"Hefei Cement Research Design Institute","ror":"https://ror.org/00kaycc68","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210100517"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jin Lin","raw_affiliation_strings":["IC Design Center, CETC No.38 Research Institute, Hefei, China"],"affiliations":[{"raw_affiliation_string":"IC Design Center, CETC No.38 Research Institute, Hefei, China","institution_ids":["https://openalex.org/I4210100517"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5007296623"],"corresponding_institution_ids":["https://openalex.org/I4210100517"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.21529833,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6683911085128784},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.6591575145721436},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6333834528923035},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5346910357475281},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.504470944404602},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5016560554504395},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.4858260154724121},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44035574793815613},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4131873846054077},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.41057419776916504},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4041096568107605},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.34862565994262695},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32807308435440063},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19537359476089478},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12667497992515564},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10858356952667236},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.08237457275390625},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.07993170619010925}],"concepts":[{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6683911085128784},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.6591575145721436},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6333834528923035},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5346910357475281},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.504470944404602},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5016560554504395},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.4858260154724121},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44035574793815613},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4131873846054077},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.41057419776916504},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4041096568107605},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.34862565994262695},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32807308435440063},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19537359476089478},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12667497992515564},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10858356952667236},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.08237457275390625},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.07993170619010925},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2015.7517162","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2015.7517162","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 11th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2073137766","https://openalex.org/W4241206086","https://openalex.org/W2081132365","https://openalex.org/W2142474790","https://openalex.org/W2398947418","https://openalex.org/W4247816723","https://openalex.org/W1964556228","https://openalex.org/W1490270176","https://openalex.org/W2000188956","https://openalex.org/W2162273398"],"abstract_inverted_index":{"This":[0,41],"paper":[1],"introduces":[2],"a":[3,8],"novel":[4],"synthesis":[5],"method":[6,42],"through":[7],"ten-million":[9],"gate":[10],"level":[11],"chip,":[12],"which":[13],"is":[14],"successfully":[15],"taped":[16],"out":[17],"and":[18,33,51],"fabricated.":[19],"By":[20],"this":[21],"method,":[22],"we":[23],"can":[24],"make":[25],"ultimate":[26],"optimization":[27],"effect":[28],"on":[29],"critical":[30],"path":[31],"design":[32],"greatly":[34],"enhance":[35],"the":[36,39,55],"performance":[37,49],"of":[38],"chip.":[40,56],"plays":[43],"an":[44],"important":[45],"role":[46],"in":[47],"achieving":[48],"goals":[50],"successful":[52],"tape-out":[53],"for":[54]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}