{"id":"https://openalex.org/W2499115071","doi":"https://doi.org/10.1109/asicon.2015.7517107","title":"100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array","display_name":"100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array","publication_year":2015,"publication_date":"2015-11-01","ids":{"openalex":"https://openalex.org/W2499115071","doi":"https://doi.org/10.1109/asicon.2015.7517107","mag":"2499115071"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2015.7517107","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2015.7517107","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 11th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100426898","display_name":"Jingjing Wang","orcid":"https://orcid.org/0000-0003-3170-8952"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Wang Jingjing","raw_affiliation_strings":["State-key Laboratory of ASIC and system, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State-key Laboratory of ASIC and system, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103777747","display_name":"Rongjin Xu","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xu Rongjin","raw_affiliation_strings":["State-key Laboratory of ASIC and system, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State-key Laboratory of ASIC and system, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051205321","display_name":"Chixiao Chen","orcid":"https://orcid.org/0000-0002-5980-4236"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chen Chixiao","raw_affiliation_strings":["State-key Laboratory of ASIC and system, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State-key Laboratory of ASIC and system, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025053306","display_name":"Fan Ye","orcid":"https://orcid.org/0000-0002-1089-1498"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ye Fan","raw_affiliation_strings":["State-key Laboratory of ASIC and system, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State-key Laboratory of ASIC and system, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100825270","display_name":"Xu Jun","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xu Jun","raw_affiliation_strings":["State-key Laboratory of ASIC and system, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State-key Laboratory of ASIC and system, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":null,"display_name":"Ren Junyan","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ren Junyan","raw_affiliation_strings":["State-key Laboratory of ASIC and system, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State-key Laboratory of ASIC and system, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5100426898"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.21234182,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10369","display_name":"Advanced MEMS and NEMS Technologies","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.8840979933738708},{"id":"https://openalex.org/keywords/spurious-free-dynamic-range","display_name":"Spurious-free dynamic range","score":0.8130478858947754},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.7563673853874207},{"id":"https://openalex.org/keywords/effective-number-of-bits","display_name":"Effective number of bits","score":0.740243136882782},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6026933789253235},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5680159330368042},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47191885113716125},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.40722474455833435},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3203543722629547},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10723245143890381}],"concepts":[{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.8840979933738708},{"id":"https://openalex.org/C119293636","wikidata":"https://www.wikidata.org/wiki/Q657480","display_name":"Spurious-free dynamic range","level":3,"score":0.8130478858947754},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.7563673853874207},{"id":"https://openalex.org/C16671190","wikidata":"https://www.wikidata.org/wiki/Q505579","display_name":"Effective number of bits","level":3,"score":0.740243136882782},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6026933789253235},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5680159330368042},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47191885113716125},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.40722474455833435},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3203543722629547},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10723245143890381}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2015.7517107","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2015.7517107","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 11th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1990158658","https://openalex.org/W2172298817","https://openalex.org/W2531538914"],"related_works":["https://openalex.org/W2759515872","https://openalex.org/W4206356469","https://openalex.org/W2904640696","https://openalex.org/W2511822798","https://openalex.org/W2341231357","https://openalex.org/W2942561789","https://openalex.org/W4390693196","https://openalex.org/W2542593952","https://openalex.org/W2207354743","https://openalex.org/W2416586275"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,25],"low":[4,102],"power":[5,88],"9-bit":[6],"100MS/s":[7],"successive":[8],"approximation":[9],"register":[10],"analog-to-digital":[11],"converter":[12],"(SAR":[13],"ADC)":[14],"due":[15],"to":[16,41,103],"the":[17,61,67,98],"custom":[18],"capacitor":[19,23,31,36,42],"array.":[20],"In":[21],"this":[22],"array,":[24],"brand-new":[26],"3-D":[27],"1-fF":[28],"MOM":[29],"unit":[30],"is":[32,51,101],"used":[33],"as":[34],"basic":[35],"cell.":[37],"A":[38],"beneficial":[39],"improvement":[40],"array":[43],"structure":[44],"makes":[45],"some":[46],"difference":[47],"too.":[48],"The":[49,95],"design":[50],"fabricated":[52],"in":[53],"TSMC":[54],"IP9M":[55],"65nm":[56],"LP":[57],"CMOS":[58],"technology.":[59],"At":[60],"same":[62],"sampling":[63],"rates":[64],"of":[65,70,77,81,85,90,97],"100MS/s,":[66],"layout":[68],"simulation":[69],"proposed":[71],"SAR":[72,99],"ADC":[73,100],"achieves":[74],"an":[75,79,83],"ENOB":[76],"8.54bit,":[78],"SNDR":[80],"53.15dB,":[82],"SFDR":[84],"63.14dB":[86],"and":[87],"consumption":[89],"0.43mW":[91],"under":[92],"Nyquist":[93],"sampling.":[94],"FOM":[96],"8.63fJ/conv.":[104]},"counts_by_year":[],"updated_date":"2026-04-16T08:26:57.006410","created_date":"2025-10-10T00:00:00"}
