{"id":"https://openalex.org/W2487506327","doi":"https://doi.org/10.1109/asicon.2015.7517072","title":"A method of automatic sizing logic driver of 16nm Fin-FET","display_name":"A method of automatic sizing logic driver of 16nm Fin-FET","publication_year":2015,"publication_date":"2015-11-01","ids":{"openalex":"https://openalex.org/W2487506327","doi":"https://doi.org/10.1109/asicon.2015.7517072","mag":"2487506327"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2015.7517072","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2015.7517072","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 11th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"ZengFa Peng","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"ZengFa Peng","raw_affiliation_strings":["Spreadtrum Co., Ltd., Suzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Spreadtrum Co., Ltd., Suzhou, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102028755","display_name":"Jian-Bin Zheng","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"JianBin Zheng","raw_affiliation_strings":["Spreadtrum Co., Ltd., Suzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Spreadtrum Co., Ltd., Suzhou, China","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101559302","display_name":"Ailin Zhang","orcid":"https://orcid.org/0000-0001-9940-7430"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"AiLin Zhang","raw_affiliation_strings":["Spreadtrum Co., Ltd., Suzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Spreadtrum Co., Ltd., Suzhou, China","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.7681328058242798},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6712892055511475},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6455740928649902},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5213655233383179},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5106030106544495},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.5082454085350037},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4691162407398224},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4473860263824463},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4191238284111023},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3645939528942108},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23193705081939697},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19169962406158447},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1558608114719391},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11150661110877991}],"concepts":[{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.7681328058242798},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6712892055511475},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6455740928649902},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5213655233383179},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5106030106544495},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.5082454085350037},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4691162407398224},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4473860263824463},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4191238284111023},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3645939528942108},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23193705081939697},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19169962406158447},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1558608114719391},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11150661110877991},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2015.7517072","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2015.7517072","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 11th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.800000011920929}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1590842594","https://openalex.org/W2090418340","https://openalex.org/W2103288275","https://openalex.org/W2108114269","https://openalex.org/W2145750057","https://openalex.org/W2156542389","https://openalex.org/W2536803352","https://openalex.org/W2536886358","https://openalex.org/W4242990199","https://openalex.org/W6635215854","https://openalex.org/W6675422573","https://openalex.org/W6728795750"],"related_works":["https://openalex.org/W2375311683","https://openalex.org/W2366062860","https://openalex.org/W2373777250","https://openalex.org/W2353956655","https://openalex.org/W1517606667","https://openalex.org/W2081032080","https://openalex.org/W2134733504","https://openalex.org/W2144460576","https://openalex.org/W2891188466","https://openalex.org/W2226796451"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3,73,83,92,112],"study":[4],"the":[5,17,31,38,47,55,61,70,94,97,114,120,124],"optimal":[6,24,116],"design":[7,25],"of":[8,26,42,88,99,123],"drivers":[9,27,62,76],"for":[10],"high":[11,39,86],"performance":[12,87],"VLSI":[13],"system":[14],"based":[15,118],"on":[16,119],"advanced":[18],"16nm":[19],"Fin-FET":[20],"logic":[21],"process.":[22],"The":[23],"is":[28],"important":[29],"to":[30],"high-speed":[32],"lower":[33],"power":[34],"VLSI,":[35],"such":[36],"as":[37],"speed":[40],"bus":[41],"processor,":[43],"clock":[44],"network":[45],"and":[46,82],"critical":[48],"signals":[49],"in":[50],"SOC":[51],"system.":[52],"Different":[53],"from":[54],"well":[56],"known":[57],"method":[58,81],"which":[59],"optimize":[60,74],"using":[63],"a":[64],"fixed":[65],"size-ratio":[66],"e(=":[67],"2.73)":[68],"between":[69],"neighbor":[71],"inverters,":[72],"sizing":[75],"efficiently":[77],"by":[78],"an":[79],"automatic":[80],"will":[84],"get":[85],"inverter":[89],"chain.":[90],"Firstly,":[91],"derive":[93],"relationship":[95,122],"among":[96],"parameters":[98],"delay,":[100],"driver":[101,105,115],"size":[102],"(fin":[103],"numbers),":[104],"stages,":[106],"input/output":[107],"(or":[108],"interconnect)":[109],"loading.":[110],"Then,":[111],"construct":[113],"tool":[117],"parameters'":[121],"driver.":[125]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}