{"id":"https://openalex.org/W2488679488","doi":"https://doi.org/10.1109/asicon.2015.7517071","title":"A DPA resistant dual rail Pr\u00e9charg\u00e9 logic cell","display_name":"A DPA resistant dual rail Pr\u00e9charg\u00e9 logic cell","publication_year":2015,"publication_date":"2015-11-01","ids":{"openalex":"https://openalex.org/W2488679488","doi":"https://doi.org/10.1109/asicon.2015.7517071","mag":"2488679488"},"language":"fr","primary_location":{"id":"doi:10.1109/asicon.2015.7517071","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2015.7517071","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 11th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Xiao Pang","orcid":null},"institutions":[{"id":"https://openalex.org/I204983213","display_name":"Harbin Institute of Technology","ror":"https://ror.org/01yqg2h08","country_code":"CN","type":"education","lineage":["https://openalex.org/I204983213"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiao Pang","raw_affiliation_strings":["Microelectronics Center, Harbin Institute of Technology at Weihai, Weihai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronics Center, Harbin Institute of Technology at Weihai, Weihai, China","institution_ids":["https://openalex.org/I204983213"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101885868","display_name":"Wang Jing","orcid":"https://orcid.org/0009-0008-6794-0255"},"institutions":[{"id":"https://openalex.org/I204983213","display_name":"Harbin Institute of Technology","ror":"https://ror.org/01yqg2h08","country_code":"CN","type":"education","lineage":["https://openalex.org/I204983213"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jing Wang","raw_affiliation_strings":["Microelectronics Center, Harbin Institute of Technology at Weihai, Weihai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronics Center, Harbin Institute of Technology at Weihai, Weihai, China","institution_ids":["https://openalex.org/I204983213"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087342788","display_name":"C.P. Wang","orcid":"https://orcid.org/0000-0003-1820-1583"},"institutions":[{"id":"https://openalex.org/I204983213","display_name":"Harbin Institute of Technology","ror":"https://ror.org/01yqg2h08","country_code":"CN","type":"education","lineage":["https://openalex.org/I204983213"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chenxu Wang","raw_affiliation_strings":["Microelectronics Center, Harbin Institute of Technology at Weihai, Weihai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronics Center, Harbin Institute of Technology at Weihai, Weihai, China","institution_ids":["https://openalex.org/I204983213"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5115547209","display_name":"Xinsheng Wang","orcid":"https://orcid.org/0000-0002-7528-4621"},"institutions":[{"id":"https://openalex.org/I204983213","display_name":"Harbin Institute of Technology","ror":"https://ror.org/01yqg2h08","country_code":"CN","type":"education","lineage":["https://openalex.org/I204983213"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xinsheng Wang","raw_affiliation_strings":["Microelectronics Center, Harbin Institute of Technology at Weihai, Weihai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronics Center, Harbin Institute of Technology at Weihai, Weihai, China","institution_ids":["https://openalex.org/I204983213"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I204983213"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"39","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":0.9797000288963318,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9491000175476074,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.7020574808120728},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6583683490753174},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.6580386161804199},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6572037935256958},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6570563316345215},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6019891500473022},{"id":"https://openalex.org/keywords/countermeasure","display_name":"Countermeasure","score":0.5469850897789001},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.5043166875839233},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4938822388648987},{"id":"https://openalex.org/keywords/emitter-coupled-logic","display_name":"Emitter-coupled logic","score":0.4587678015232086},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.4576408565044403},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.45232874155044556},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.44826728105545044},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44167888164520264},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.41482385993003845},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3677715063095093},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.23534807562828064},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20830124616622925},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.142643004655838},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09304723143577576},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.06608915328979492}],"concepts":[{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.7020574808120728},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6583683490753174},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.6580386161804199},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6572037935256958},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6570563316345215},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6019891500473022},{"id":"https://openalex.org/C21593369","wikidata":"https://www.wikidata.org/wiki/Q1032176","display_name":"Countermeasure","level":2,"score":0.5469850897789001},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.5043166875839233},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4938822388648987},{"id":"https://openalex.org/C11644886","wikidata":"https://www.wikidata.org/wiki/Q173552","display_name":"Emitter-coupled logic","level":5,"score":0.4587678015232086},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.4576408565044403},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.45232874155044556},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.44826728105545044},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44167888164520264},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.41482385993003845},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3677715063095093},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.23534807562828064},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20830124616622925},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.142643004655838},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09304723143577576},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.06608915328979492},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C146978453","wikidata":"https://www.wikidata.org/wiki/Q3798668","display_name":"Aerospace engineering","level":1,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2015.7517071","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2015.7517071","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 11th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1569380263","https://openalex.org/W1575446397","https://openalex.org/W1607006990","https://openalex.org/W2016763699","https://openalex.org/W2116406812","https://openalex.org/W2144630005","https://openalex.org/W2154909745"],"related_works":["https://openalex.org/W2017528947","https://openalex.org/W2001164331","https://openalex.org/W2096007426","https://openalex.org/W4206656053","https://openalex.org/W1983370375","https://openalex.org/W4231710159","https://openalex.org/W2167525841","https://openalex.org/W2101829379","https://openalex.org/W4214510975","https://openalex.org/W1941788997"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,45],"novel":[4],"differential":[5,55],"pass-transistor":[6,14],"precharge":[7],"logic":[8,15,56],"(DPPL)":[9],"based":[10],"on":[11],"the":[12,18,23,35,52,79],"complementary":[13],"(CPL).":[16],"In":[17],"aspect":[19],"of":[20,26,37,65,86],"circuit-level":[21],"countermeasure,":[22],"power":[24,59,80],"consumption":[25],"DPPL":[27,32,66,87],"is":[28],"more":[29],"constant.":[30],"The":[31,58,75],"also":[33],"solves":[34],"problem":[36],"early":[38],"propagation":[39],"effects":[40],"(EPE)":[41],"effectively":[42],"and":[43,61,82],"has":[44],"relatively":[46],"small":[47],"area":[48],"overhead":[49],"compared":[50],"to":[51,90],"wave":[53],"dynamic":[54],"(WDDL).":[57],"constancy":[60,81],"DPA":[62,83],"resistant":[63,84],"capability":[64,85],"are":[67,88],"evaluated":[68],"by":[69],"SPICE":[70],"simulation":[71],"in":[72],"this":[73],"paper.":[74],"results":[76],"show":[77],"that":[78],"superior":[89],"WDDL.":[91]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
