{"id":"https://openalex.org/W2484216599","doi":"https://doi.org/10.1109/asicon.2015.7516939","title":"Sample-hold circuit and stage circuits in a traditional 12-b 80-Msample/s pipelined A/D converter","display_name":"Sample-hold circuit and stage circuits in a traditional 12-b 80-Msample/s pipelined A/D converter","publication_year":2015,"publication_date":"2015-11-01","ids":{"openalex":"https://openalex.org/W2484216599","doi":"https://doi.org/10.1109/asicon.2015.7516939","mag":"2484216599"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2015.7516939","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2015.7516939","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 11th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052852912","display_name":"Xiangqian Jiang","orcid":"https://orcid.org/0000-0001-7949-8507"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xiang Jiang","raw_affiliation_strings":["Department of Microelectronics, Xi'anJiaotong University, Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, Xi'anJiaotong University, Xi'an, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065201436","display_name":"Jun Cheng","orcid":"https://orcid.org/0000-0002-7771-2132"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun Cheng","raw_affiliation_strings":["Department of Microelectronics, Xi'anJiaotong University, Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, Xi'anJiaotong University, Xi'an, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100420703","display_name":"Liang Li","orcid":"https://orcid.org/0000-0003-0708-7762"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Liang Li","raw_affiliation_strings":["Science and Technology on Analog Integrated Circuit Laboratory, Chongqing, China"],"affiliations":[{"raw_affiliation_string":"Science and Technology on Analog Integrated Circuit Laboratory, Chongqing, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100458294","display_name":"Ting Zhang","orcid":"https://orcid.org/0000-0002-0258-2003"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ting Zhang","raw_affiliation_strings":["Department of Microelectronics, Xi'anJiaotong University, Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, Xi'anJiaotong University, Xi'an, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050159482","display_name":"Liao Gong","orcid":null},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liao Gong","raw_affiliation_strings":["Department of Microelectronics, Xi'anJiaotong University, Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, Xi'anJiaotong University, Xi'an, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049721531","display_name":"Qiyun Ma","orcid":"https://orcid.org/0000-0002-3065-094X"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qiyun Ma","raw_affiliation_strings":["Department of Microelectronics, Xi'anJiaotong University, Xi'an, China"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, Xi'anJiaotong University, Xi'an, China","institution_ids":["https://openalex.org/I87445476"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5052852912"],"corresponding_institution_ids":["https://openalex.org/I87445476"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.20817786,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.9861999750137329,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5615264177322388},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5573340654373169},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.5209032893180847},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.4817638397216797},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4678787589073181},{"id":"https://openalex.org/keywords/sample-and-hold","display_name":"Sample and hold","score":0.425694078207016},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.38954177498817444},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.3710019886493683},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26964065432548523},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.20874276757240295}],"concepts":[{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5615264177322388},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5573340654373169},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.5209032893180847},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.4817638397216797},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4678787589073181},{"id":"https://openalex.org/C206565188","wikidata":"https://www.wikidata.org/wiki/Q836482","display_name":"Sample and hold","level":3,"score":0.425694078207016},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.38954177498817444},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.3710019886493683},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26964065432548523},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.20874276757240295}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2015.7516939","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2015.7516939","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 11th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1566916904","https://openalex.org/W2071761885"],"related_works":["https://openalex.org/W2181172762","https://openalex.org/W2390607226","https://openalex.org/W2147177175","https://openalex.org/W2018705424","https://openalex.org/W2393658466","https://openalex.org/W2119867448","https://openalex.org/W2383563100","https://openalex.org/W3128753656","https://openalex.org/W4297192903","https://openalex.org/W1578989561"],"abstract_inverted_index":{"The":[0,15,62,131,152],"front":[1],"sample-hold":[2,16],"circuit":[3,7,17,72,96,117,146],"and":[4,18,70,84,89,99,143],"each":[5,43,71],"stage":[6,19],"are":[8,28,67,82,87,118],"the":[9,34,40,45,53,74,94,102,109,112,128,135,144],"heart":[10],"of":[11,36,42,47,55,64,93,101,115,134,150],"traditional":[12,23],"pipelined":[13,26],"ADC[1].":[14],"circuits":[20,49],"in":[21,30,121],"a":[22,160],"12-b":[24],"80-Msample/s":[25],"ADC":[27,137],"presented":[29],"this":[31,122],"paper.":[32],"Under":[33],"condition":[35],"serious":[37],"analysis":[38],"about":[39,139,157],"principle":[41],"stage,":[44],"design":[46,59,75,129],"core":[48,145],"is":[50,60,97,105,138,156],"finished.":[51],"Using":[52],"process":[54],"chartered":[56],"180nm,":[57],"layout":[58,132],"done.":[61],"results":[63,114],"post-layout":[65],"simulations":[66],"pretty":[68],"good":[69],"meets":[73],"demand.":[76,130],"Two":[77],"op-amps":[78],"with":[79],"high":[80],"performance":[81],"designed":[83],"gain-bandwidth":[85],"products":[86],"819.8MHz":[88],"1.726GHz":[90],"respectively.":[91],"SNDR":[92,100],"S&H":[95],"91.41dB":[98],"first":[103],"3.5b/stage":[104],"77.84dB.":[106],"Due":[107],"to":[108],"space":[110],"limitation,":[111],"simulation":[113],"other":[116],"not":[119],"mentioned":[120],"paper,":[123],"but":[124],"they":[125],"all":[126],"meet":[127],"area":[133],"whole":[136,153],"2.2mm":[140],"\u00d7":[141],"1.7mm":[142],"accounts":[147],"for":[148],"two-thirds":[149],"it.":[151],"power":[154,163],"consumption":[155],"460mW":[158],"from":[159],"3.3":[161],"V":[162],"supply.":[164]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
