{"id":"https://openalex.org/W2479312088","doi":"https://doi.org/10.1109/asicon.2015.7516905","title":"Clock skew estimate modeling for FPGA high-level synthesis and its application","display_name":"Clock skew estimate modeling for FPGA high-level synthesis and its application","publication_year":2015,"publication_date":"2015-11-01","ids":{"openalex":"https://openalex.org/W2479312088","doi":"https://doi.org/10.1109/asicon.2015.7516905","mag":"2479312088"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2015.7516905","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2015.7516905","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 11th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048571648","display_name":"Koichi Fujiwara","orcid":null},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Koichi Fujiwara","raw_affiliation_strings":["Department of Computer Science and Communication Engineering, Waseda University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Communication Engineering, Waseda University","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002692556","display_name":"Kazushi Kawamura","orcid":"https://orcid.org/0000-0002-0795-2974"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kazushi Kawamura","raw_affiliation_strings":["Department of Computer Science and Communication Engineering, Waseda University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Communication Engineering, Waseda University","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061982025","display_name":"Masao Yanagisawa","orcid":"https://orcid.org/0000-0002-5168-3214"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masao Yanagisawa","raw_affiliation_strings":["Department of Computer Science and Communication Engineering, Waseda University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Communication Engineering, Waseda University","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087516286","display_name":"Nozomu Togawa","orcid":"https://orcid.org/0000-0003-3400-3587"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Nozomu Togawa","raw_affiliation_strings":["Department of Computer Science and Communication Engineering, Waseda University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Communication Engineering, Waseda University","institution_ids":["https://openalex.org/I150744194"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I150744194"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8408008813858032},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.7005059719085693},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6741889715194702},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6696404218673706},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6655415296554565},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.6414352655410767},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.5644811391830444},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5134254693984985},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.495449423789978},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.48157310485839844},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.47635698318481445},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.43190568685531616},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.42577099800109863},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.1739387810230255},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.08547422289848328}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8408008813858032},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.7005059719085693},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6741889715194702},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6696404218673706},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6655415296554565},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.6414352655410767},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.5644811391830444},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5134254693984985},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.495449423789978},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.48157310485839844},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.47635698318481445},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.43190568685531616},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.42577099800109863},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.1739387810230255},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.08547422289848328},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2015.7516905","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2015.7516905","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 11th International Conference on ASIC (ASICON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2003610890","https://openalex.org/W2007252437","https://openalex.org/W2047631674","https://openalex.org/W2073137766","https://openalex.org/W2119191999","https://openalex.org/W2158566102","https://openalex.org/W2171413119","https://openalex.org/W4235515009","https://openalex.org/W6677974672"],"related_works":["https://openalex.org/W4247089581","https://openalex.org/W2133326759","https://openalex.org/W4247180033","https://openalex.org/W2088914741","https://openalex.org/W4230501858","https://openalex.org/W1564063853","https://openalex.org/W1938797020","https://openalex.org/W2003180247","https://openalex.org/W1525888526","https://openalex.org/W60672686"],"abstract_inverted_index":{"Recently,":[0],"high-level":[1],"synthesis":[2],"(HLS)":[3],"techniques":[4],"for":[5,49],"FPGA":[6,16,74,85],"designs":[7,86],"are":[8],"required":[9],"in":[10,15,61],"various":[11],"applications.":[12],"Clock":[13],"network":[14],"has":[17],"already":[18],"been":[19],"built":[20],"before":[21],"implementing":[22],"any":[23],"circuits,":[24],"which":[25,87],"may":[26],"lead":[27],"a":[28,44,69],"large":[29],"impact":[30],"of":[31],"clock":[32,45,59],"skews":[33,60],"and":[34],"then":[35,66],"degrade":[36],"operation":[37],"frequency.":[38],"In":[39],"this":[40],"paper,":[41],"we":[42],"formulate":[43],"skew":[46],"estimate":[47,58],"model":[48,56],"FPGA-HLS":[50],"(CSEF).":[51],"CSEF":[52,64],"is":[53,65],"an":[54],"accurate":[55],"to":[57,93],"HLS":[62,71,81],"flow.":[63],"integrated":[67],"into":[68],"floorplan-aware":[70],"algorithm":[72,82],"targeting":[73],"designs.":[75],"Experimental":[76],"results":[77],"demonstrate":[78],"that":[79],"our":[80],"can":[83],"realize":[84],"reduce":[88],"the":[89],"latency":[90],"by":[91],"up":[92],"19%":[94],"compared":[95],"with":[96],"conventional":[97],"approaches.":[98]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}