{"id":"https://openalex.org/W2096096308","doi":"https://doi.org/10.1109/asicon.2013.6812042","title":"Mixed-signal verification methods for multi-power mixed-signal System-on-Chip (SoC) design","display_name":"Mixed-signal verification methods for multi-power mixed-signal System-on-Chip (SoC) design","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W2096096308","doi":"https://doi.org/10.1109/asicon.2013.6812042","mag":"2096096308"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2013.6812042","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2013.6812042","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 10th International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029077773","display_name":"Chao Liang","orcid":"https://orcid.org/0000-0001-7141-3759"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Chao Liang","raw_affiliation_strings":["Microcontroller Group, Freescale, Suzhou, China","Microcontroller Group, Freescale, Suzhou 215011, China"],"affiliations":[{"raw_affiliation_string":"Microcontroller Group, Freescale, Suzhou, China","institution_ids":[]},{"raw_affiliation_string":"Microcontroller Group, Freescale, Suzhou 215011, China","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5029077773"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.8913,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.86340505,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6958192586898804},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.6744117736816406},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.6316683888435364},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6126147508621216},{"id":"https://openalex.org/keywords/microcontroller","display_name":"Microcontroller","score":0.5930657386779785},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5525543093681335},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5170822143554688},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.5041118860244751},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4982569217681885},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.49506011605262756},{"id":"https://openalex.org/keywords/high-level-verification","display_name":"High-level verification","score":0.4719768166542053},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.45023900270462036},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.42914339900016785},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.42807018756866455},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39581751823425293},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.19497257471084595},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18735763430595398},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.102200448513031},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.0797690749168396}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6958192586898804},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.6744117736816406},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.6316683888435364},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6126147508621216},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.5930657386779785},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5525543093681335},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5170822143554688},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.5041118860244751},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4982569217681885},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.49506011605262756},{"id":"https://openalex.org/C187250869","wikidata":"https://www.wikidata.org/wiki/Q5754573","display_name":"High-level verification","level":5,"score":0.4719768166542053},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.45023900270462036},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.42914339900016785},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.42807018756866455},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39581751823425293},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.19497257471084595},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18735763430595398},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.102200448513031},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0797690749168396},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2013.6812042","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2013.6812042","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 10th International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5299999713897705,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2161838824"],"related_works":["https://openalex.org/W2361881307","https://openalex.org/W2392047570","https://openalex.org/W4205300843","https://openalex.org/W2929969821","https://openalex.org/W3155012083","https://openalex.org/W2354470518","https://openalex.org/W3120172095","https://openalex.org/W2059150015","https://openalex.org/W2162314935","https://openalex.org/W2087184054"],"abstract_inverted_index":{"Mixed-signal":[0],"design":[1,28,66],"becomes":[2],"more":[3,5,43,45],"and":[4,20,24,44,55,64,111],"popular":[6],"nowadays":[7],"because":[8],"designers":[9],"are":[10,41,118],"required":[11],"to":[12,30,60,71,120],"quickly":[13],"integrate":[14],"IPs,":[15],"control":[16],"blocks,":[17,19],"functional":[18,114],"analog":[21],"modules":[22],"together":[23],"run":[25],"through":[26],"the":[27,38,47,73,76,122],"flow":[29,67],"tape":[31],"out":[32],"in":[33,51],"short":[34],"time.":[35],"Given":[36],"that":[37],"latest":[39],"designs":[40],"becoming":[42],"complex,":[46],"increasing":[48],"physical":[49],"effects":[50],"advanced":[52],"process":[53],"nodes,":[54],"request":[56],"for":[57],"shorter":[58],"time":[59],"market,":[61],"a":[62],"fast":[63],"accurate":[65],"will":[68,80],"be":[69],"critical":[70],"ensure":[72],"success":[74],"of":[75,124],"project.":[77],"This":[78],"paper":[79],"briefly":[81],"describe":[82],"various":[83],"mixed":[84,112],"signal":[85,113],"verification":[86],"methods":[87],"used":[88],"at":[89],"Freescale":[90],"Kinetis":[91],"MCU":[92],"which":[93],"include":[94],"behavior":[95],"modeling,":[96],"AMS":[97],"validation,":[98],"connectivity":[99],"verification,":[100,106],"mixed-signal":[101],"Verification":[102],"IP":[103],"(VIP),":[104],"multi-power":[105],"SoC":[107],"transistor":[108],"level":[109],"simulation":[110],"coverage.":[115],"Engineering":[116],"results":[117],"discussed":[119],"demonstrate":[121],"effectiveness":[123],"those":[125],"methods.":[126]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2017,"cited_by_count":3},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}