{"id":"https://openalex.org/W2564362016","doi":"https://doi.org/10.1109/asicon.2013.6812030","title":"FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp","display_name":"FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W2564362016","doi":"https://doi.org/10.1109/asicon.2013.6812030","mag":"2564362016"},"language":"en","primary_location":{"id":"doi:10.1109/asicon.2013.6812030","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2013.6812030","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 10th International Conference on ASIC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100633766","display_name":"Minghua Li","orcid":"https://orcid.org/0000-0002-7857-6670"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Minghua Li","raw_affiliation_strings":["Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054960059","display_name":"Dian Zhou","orcid":"https://orcid.org/0000-0002-2648-5232"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dian Zhou","raw_affiliation_strings":["Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114310084","display_name":"Sheng-Guo Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I102149020","display_name":"University of North Carolina at Charlotte","ror":"https://ror.org/04dawnj30","country_code":"US","type":"education","lineage":["https://openalex.org/I102149020"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sheng-Guo Wang","raw_affiliation_strings":["Department of Engineering Technology, University of North Carolina at Charlotte, NC, USA"],"affiliations":[{"raw_affiliation_string":"Department of Engineering Technology, University of North Carolina at Charlotte, NC, USA","institution_ids":["https://openalex.org/I102149020"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064213921","display_name":"Xuan Zeng","orcid":"https://orcid.org/0000-0002-8097-4053"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xuan Zeng","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100633766"],"corresponding_institution_ids":["https://openalex.org/I162577319"],"apc_list":null,"apc_paid":null,"fwci":0.2393,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.65663447,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"1","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transconductance","display_name":"Transconductance","score":0.7600693702697754},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.5914676785469055},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.5738246440887451},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5434184670448303},{"id":"https://openalex.org/keywords/operational-transconductance-amplifier","display_name":"Operational transconductance amplifier","score":0.4806622266769409},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4753308594226837},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.46766436100006104},{"id":"https://openalex.org/keywords/process-design","display_name":"Process design","score":0.46600207686424255},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.44815054535865784},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42272502183914185},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.4122087061405182},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.37217870354652405},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.35994356870651245},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2432907521724701},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21174821257591248},{"id":"https://openalex.org/keywords/process-integration","display_name":"Process integration","score":0.15903350710868835},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.1203913688659668},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07565143704414368}],"concepts":[{"id":"https://openalex.org/C2779283907","wikidata":"https://www.wikidata.org/wiki/Q1632964","display_name":"Transconductance","level":4,"score":0.7600693702697754},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.5914676785469055},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.5738246440887451},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5434184670448303},{"id":"https://openalex.org/C58117264","wikidata":"https://www.wikidata.org/wiki/Q1239595","display_name":"Operational transconductance amplifier","level":5,"score":0.4806622266769409},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4753308594226837},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.46766436100006104},{"id":"https://openalex.org/C55396564","wikidata":"https://www.wikidata.org/wiki/Q3084971","display_name":"Process design","level":3,"score":0.46600207686424255},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.44815054535865784},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42272502183914185},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.4122087061405182},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.37217870354652405},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.35994356870651245},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2432907521724701},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21174821257591248},{"id":"https://openalex.org/C54725748","wikidata":"https://www.wikidata.org/wiki/Q7247277","display_name":"Process integration","level":2,"score":0.15903350710868835},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.1203913688659668},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07565143704414368},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C21880701","wikidata":"https://www.wikidata.org/wiki/Q2144042","display_name":"Process engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/asicon.2013.6812030","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asicon.2013.6812030","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 10th International Conference on ASIC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5299999713897705,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320321851","display_name":"Fudan University","ror":"https://ror.org/013q1eq08"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1502034973","https://openalex.org/W1552715261","https://openalex.org/W2006944925","https://openalex.org/W2010266312","https://openalex.org/W2029021634","https://openalex.org/W2065161569","https://openalex.org/W2100947672","https://openalex.org/W2108613929","https://openalex.org/W2131917361","https://openalex.org/W2151589511","https://openalex.org/W2158338310","https://openalex.org/W2543452827","https://openalex.org/W6990048105"],"related_works":["https://openalex.org/W2783539788","https://openalex.org/W4293528144","https://openalex.org/W2792031931","https://openalex.org/W2341419291","https://openalex.org/W3113698884","https://openalex.org/W2074850648","https://openalex.org/W2953413763","https://openalex.org/W2556688074","https://openalex.org/W1530143999","https://openalex.org/W4225146906"],"abstract_inverted_index":{"This":[0,34],"paper":[1],"presents":[2],"a":[3,15,61,67],"robust":[4],"design":[5,17,35],"and":[6],"global":[7],"optimization":[8],"methodology":[9],"for":[10],"Rail-to-Rail":[11],"operational":[12],"amplifier":[13],"using":[14],"computer-aided":[16],"(CAD)":[18],"tool":[19],"called":[20],"FMSSQP.":[21],"Performance":[22],"parameters":[23],"are":[24,53],"optimized":[25],"while":[26],"the":[27,72],"impact":[28],"of":[29,63],"process":[30,51],"variation":[31],"is":[32,36],"minimized.":[33],"implemented":[37],"with":[38,71],"0.25-\u00b5m":[39],"CMOS":[40],"process.":[41],"The":[42],"result":[43],"shows":[44],"that":[45],"transconductance":[46],"(gm)":[47],"variations":[48],"at":[49],"each":[50],"corners":[52],"less":[54],"than":[55],"7%,":[56],"circuit":[57],"performance":[58],"presented":[59],"by":[60],"Figure":[62],"Merit":[64],"(FOM)":[65],"has":[66],"significant":[68],"improvement":[69],"compared":[70],"published":[73],"works.":[74]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
